Up to now we were able to read/write environment data from/to UBI
volumes only indirectly by gluebi driver. This driver creates NAND MTD
on top of UBI volumes, which is quite a workaroung for this use case.

Add support for direct read/write UBI volumes in order to not use
obsolete gluebi driver.

Forward-ported from this patch:
http://patchwork.ozlabs.org/patch/619305/



Original patch:
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>

Forward port:
Signed-off-by: S. Lockwood-Childs <sjl@vctlabs.com>

AE3XX can not support SD high-speed mode.
SW can work-around by removing HS capibility.

Signed-off-by: Rick Chen <rick@andestech.com>

Bit of DATA_END and DATA_CRC_OK shall be checked for
returning pass or fail of a request.

Signed-off-by: Rick Chen <rick@andestech.com>

AG101P/AE3XX enable ftsdc010 dm flow.

Signed-off-by: Rick Chen <rick@andestech.com>

Add dts to support ftsdc010 dm flow on AG101P/AE3XX platform.

Signed-off-by: Rick Chen <rick@andestech.com>

ftsdc010 support device tree flow.

Signed-off-by: Rick Chen <rick@andestech.com>

Add nds32_mmc to support ftsdc010 dm flow.

Signed-off-by: Rick Chen <rick@andestech.com>

Add a document to describe Andestech atcspi200 spi and
binding information.

Signed-off-by: Rick Chen <rick@andestech.com>

Integrate function and struct name from ae3xx to
atcspi200 will be more reasonable.

Signed-off-by: Rick Chen <rick@andestech.com>

atcspi200 is Andestech spi ip which is embedded in
AE3XX and AE250 platforms. So rename as atcspi200
will be more reasonable to be used in different
platforms.

Signed-off-by: Rick Chen <rick@andestech.com>

ATCPIT100 is often used in AE3XX platform which is
based on NDS32 architecture recently. But in the future
Andestech will have AE250 platform which is embeded
ATCPIT100 timer based on RISCV architecture.

Signed-off-by: Rick Chen <rick@andestech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Add a document to describe Andestech atcpit100 timer and
binding information.

Signed-off-by: rick <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Use dev_get_platdata to get private platdata.

Signed-off-by: rick <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Integrate function and struct name as atcpit100 will be
more reasonable.

Signed-off-by: rick <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

ATCPIT100 is Andestech timer IP which is embeded
in AE3XX and AE250 boards. So rename AE3XX to
ATCPIT100 will be more make sence.

Signed-off-by: rick <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

It will be work fine with unsigned long declaretion in timer
register struct when system is 32 bit. But it will not work
well when system is 64 bit. Replace it by u32 and verify both
ok in 32/64 bit.

Signed-off-by: Rick Chen <rick@andestech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

Xilinx changes for v2018.1

Zynq:
- Add support for Syzygy and cc108 boards
- Add support for mini u-boot configurations (cse)
- dts updates
- config/defconfig updates in connection to Kconfig changes
- Fix psu_init handling

ZynqMP:
- SPL fixes
- Remove slcr.c
- Fixing r5 startup sequence
- Add support for external pmufw
- Add support for new ZynqMP chips
- dts updates
- Add support for zcu102 rev1.0 board

Drivers:
- nand: Support external timing setting and board init
- ahci: Fix wording
- axi_emac: Wait for bit, non processor mode, readl/write conversion
- zynq_gem: Fix SGMII/PCS support

This patch uses readl and writel instead of in_be32 and
out_be32 for io ops as these internally uses readl,
writel for microblaze and for Zynq, ZynqMP there is
no need of endianness conversion and readl, writel
should work straightaway. This patch starts supporting
the driver for Zynq and ZynqMP platforms.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Dont enable SGMII and PCS selection if internal PCS/PMA
is not used, by getting the info about internal/external
PCS/PMA usage from dt property "is-internal-phy".

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Use more accurate description for Xilinx Zynq and ZynqMP based platforms.
With using driver model there shouldn't be a need to create separate
Kconfig config options.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

The chapter in which the table explaining the image format changed
chapter as the document evolved. This should help people track the
info down faster.

Signed-off-by: Jean-Francois Dagenais <jeff.dagenais@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Zynq NAND driver is not support for NAND lock or unlock operation.
Hence, accidentally write into the critical NAND region might cause
data corruption to occur.

This commit is to add NAND lock/unlock command into NAND SMC register
set for NAND lock/unlock operaion.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Keng Soon Cheah <keng.soon.cheah@ni.com>
Cc: Chen Yee Chew <chen.yee.chew@ni.com>
Cc: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Scott Wood <oss@buserror.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Putting board_nand_init() function inside NAND driver was not appropriate
due to it doesn't allow board vendor to customise their NAND
initialization code such as adding NAND lock/unlock code.

This commit was to move the board_nand_init() function from NAND driver
to board.c file. This allow customization of board_nand_init() function.

Signed-off-by: Wilson Lee <wilson.lee@ni.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Keng Soon Cheah <keng.soon.cheah@ni.com>
Cc: Chen Yee Chew <chen.yee.chew@ni.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Cc: Scott Wood <oss@buserror.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

After some generic cleanup adding ps7_init* to repository
is not big pain now.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Show information about silicon in bootlog.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

There is no reason to show information about board twice.
Remove boardinfo late calls.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Sparse is return warning about this:
arch/arm/mach-zynq/slcr.c: In function 'zynq_slcr_get_mio_pin_status':
arch/arm/mach-zynq/slcr.c:185:16: warning: comparison between signed and
unsigned integer expressions [-Wsign-compare]
  for (i = 0; i < ARRAY_SIZE(mio_periphs); i++) {
                ^

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Use generic implementation. It will also reduce config data size for
converted boards.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Add proper support for EMIT_WRITE operation which is write only.
Do not use EMIT_MASKWRITE which is read-modify-write.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Unfortunately camelcase is coming from ps7_init* format.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

This patch is based on work done in topic board where the first address
word also storing operation which should be done. This is reducing size
of configuration data.
This patch is not breaking an option to copy default ps7_init_gpl* files
from hdf file but it is doing preparation for ps7_init* consolidation.

The patch is also marking ps7_config as weak function.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

There is no reason to call separate function.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Extract ps7_* from spl code to prepare for extension.
And also return value.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

SPL is not calling this code that's why it is dead code and can be
removed.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Enable debug uart by default.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Add missing declaration to header.

Warning log:
arch/arm/mach-zynq/spl.c:94:12: warning: symbol 'ps7_post_config' was
not declared. Should it be static?

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Add support for non processor mode, this mode doesn't have
access to some of the registers and hence this patch
bypasses it and also length has to be calculated from
status instead of app4 in this mode.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>