Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>

Aspenite is a Development Board for ASPEN/ARMADA168(88AP168) with
	* Processor upto 1.2GHz
        * Parallel 1Gb x8 DDR2-1066 MHz
        * 16 Mb x16 NOR, 4Gb x8 SLC NAND, footprint for SPI NOR
        * Footprints for eMMC/eSD NAND & MMC x8 card
        * 4-in-1 card reader (xD, MMC/SD/MS Pro), CF True IDE socket
        * SEAF memory board, subset of PISMO2
    With Peripherals:
        * 4.3” WVGA 24-bit LCD
        * Audio codecs (AC97 & I2S), TSI
        * VGA camera
        * Video in via 3 RCA jacks, and HDMI type C out
        * Marvell 88W8688 802.11bg/BT module
        * GPS RF IC
        * Dual analog mics & speakers, headset jack, LED, ambient light sensor
        * USB2.0 HS host  (A), OTG (micro AB)
        * FE PHY, PCIE Mini Card  slot
        * GPIO, GPIO expander with DIP switches for easier selection UART serial over USB, CIR

This patch adds basic board support with DRAM and UART functionality
The patch is tested for boot from DRAM using XDB

Signed-off-by: Mahavir Jain <mjain@marvell.com>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>

This patch adds commonly used macros for ARMADA100 based
baords, Also some code reshuffled and updated for typos and comments

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>

ARMADA 100 SoCs has NS16550 compatible UART peripheral
This patch enables the same for ARMADA100 platforms

Signed-off-by: Mahavir Jain <mjain@marvell.com>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>

On some processors this ier register configuration is different
for ex. Marvell Armada100

This patch introduce CONFIG_SYS_NS16550_IER macro support to
unconditionally initialize this register.

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>

This patch adds the support MFP support for Marvell ARMADA100 SoCs

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>

Most of the Marvell SoCs has Multi Function Pin (MFP) configuration registers
For ex. ARMADA100.

These registers are programmed to expose the specific functionality
associated with respective SoC Pins

This driver provides configuration APIs,
using them, configuration need to be done in board specific code

for ex- following code configures MFPs 107 and 108 for UART_TX/RX functionality

int board_early_init_f(void)
{
        u32 mfp_cfg[] = {
                /* Console on UART1 */
                MFP107_UART1_RXD,
                MFP108_UART1_TXD,
                MFP_EOC         /*End of configureation*/
        };
        /* configure MFP's */
        mfp_config(mfp_cfg);
        return 0;
}

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>

ARMADA 100 Family processors are highly integrated SoCs
based on Sheeva_88SV331x-v5 PJ1 cpu core.
Ref: http://www.marvell.com/products/processors/applications/armada_100



SoC versions Supported:
1) ARMADA168/88AP168	(Aspen P)
2) ARMADA166/88AP166	(Aspen M)
3) ARMADA162/88AP162	(Aspen L)

Contributors:
Eric Miao <eric.y.miao@gmail.com>
Lei Wen <leiwen@marvell.com>
Mahavir Jain <mjain@marvell.com>

Signed-off-by: Mahavir Jain <mjain@marvell.com>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>

- serial console in PSC1
- 128MiB DRAM
- 32MiB Flash
- FEC Ethernet
- 2 I2C busses
- FPGA on CS3
- IDE
- VGA SMI501

Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Wolfgang Denk <wd@denx.de>

Signed-off-by: Asen Dimov <dimov@ronetix.at>

Signed-off-by: Asen Dimov <dimov@ronetix.at>

Signed-off-by: Asen Dimov <dimov@ronetix.at>

Signed-off-by: Asen Dimov <dimov@ronetix.at>

Signed-off-by: Asen Dimov <dimov@ronetix.at>

Signed-off-by: Asen Dimov <dimov@ronetix.at>

This patch fixes the acadia_nand and kilauea_nand linker scripts
which have been missing in commit ee8028b7 [ppc4xx: Cleanup for
partial linking and --gc-sections]

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bernhard Weirich <Bernhard.Weirich@riedel.net>

Make code build with older tool chains.

Signed-off-by: Wolfgang Denk <wd@denx.de>

This patch fix a problem for the pcie enumeration for mpc83xx cpus.  Without
this we will not  get correct value in hose->regions[...].

The pointer *reg in function mpc83xx_pcie_init_bus() shall not be changed.
Because we will use this pointer as a parameter to call function
mpc83xx_pcie_register_hose().

Signed-off-by: Baidu Boy <liucai.lfn@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

On the P1022, the pins which drive the video display (DIU) are muxed with the
local bus controller (LBC), so if the DIU is active, the pins need to be
temporarily muxed to LBC whenever accessing NOR flash.

The code which handled this transition is checking and changing the wrong
bits in PMUXCR.

Also add a follow-up read after a write to NOR flash if we're going to
mux back to DIU after the write, as described in the P1022 RM.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

eSDHC host controller reset results in clearing of snoop bit also.
This patch sets the SNOOP bit after the completion of host controller reset.
Without this patch mmc reads are not consistent.

Signed-off-by: P.V.Suresh <pala@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

According to Freescale reference manuals (eg section "13.4.4.2
Programming the UPMs" of the P4080 Reference Manual):

"Since the result of any update to the MxMR/MDR register must be in
effect before the dummy read or write to the UPM region, a write to
MxMR/MDR should be followed immediately by a read of MxMR/MDR."

The UPM on a custom P4080-based board did not work without performing
a read of MxMR/MDR after a write.

Signed-off-by: John Schmoller <jschmoller@xes-inc.com>
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

The following commit:

commit 46e91674
Author: Peter Tyser <ptyser@xes-inc.com>
Date:   Tue Nov 3 17:52:07 2009 -0600

    tsec: Force TBI PHY to 1000Mbps full duplex in SGMII mode

Removed setting Auto-Neg by default, however this is believed to be
proper default configuration for initialization of the TBI interface.

Instead we explicitly set CONFIG_TSEC_TBICR_SETTINGS for the
XPedite5370 & XPedite5500 boards that use a Broadcomm PHY which require
Auto-Neg to be disabled to function properly.

This addresses a breakage on the P2020 DS & MPC8572 DS boards when used
with an SGMII riser card.  We also remove setting
CONFIG_TSEC_TBICR_SETTINGS on the P1_P2_RDB family of boards as now the
default setting is sufficient for them.

Additionally, we clean up the code a bit to remove an unnecessary second
define.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Peter Tyser <ptyser@xes-inc.com>
Tested-by: Peter Tyser <ptyser@xes-inc.com>

DECLARE_GLOBAL_DATA_PTR declarations in functions are inherently
troublesome with various compilers (e.g. gcc 4.5)

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

CC: Ruslan N. Araslanov <byaaka@yandex.ru>
Signed-off-by: Ruslan Araslanov <ruslan.araslanov@vitecmm.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

Add battery charging support twl6030 driver.
Add support for battery voltage and current measurements.
Add command to get battery status and start/stop battery charging from USB.

Signed-off-by: Balaji T K <balajitk@ti.com>
Tested-by: Steve Sakoman <steve.sakoman@linaro.org>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

Reuse the gd->tbl value for timestamp and add gd->lastinc for lastinc bss
values in the OMAP timer driver.

The usage of bss values in drivers before initialisation of bss is forbidden.
In that special case some data in .rel.dyn gets corrupted.

Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
Tested-by: Steve Sakoman <steve.sakoman@linaro.org>
Tested-by: John Rigby <john.rigby@linaro.org>
Tested-by: Nishanth Menon <nm@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Tested-by: Heiko Schocher <hs@denx.de>
Tested-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

The DM6446 does not build due to the ARM
relocation patch.

Also the board does not build in the NOR
mode. Changed default to NAND to ensure
no build failure.
While at it removed CONFIG_CMD_KGDB

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

This change allows the davinci timer functions to be used before
relocation since it avoids using static variables prior to BSS being
made available.

The code is based on that used in the at91 timers, modified to use
a davinci specific hardware timer. It also maintains reset_timer()
to allow deprecated timer usage to continue to work (for example,
in nand_base.c)

Signed-off-by: Nick Thompson <nick.thompson@ge.com>
Tested-by: Ben Gardiner <bengardiner@nanometrics.ca>
Tested-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Tested-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>

This file has been synced (copy) from Linux source code.
This commit was based on kernel 2.6.32.
It updates gigabit related phy registers and basic definitions.

Signed-off-by: Macpaul Lin <macpaul@andestech.com>

All code that attemots to access variables in BSS before relocation
(for example directly or indirectly by board_init_f()) needs to be
fixed. Especially timer.c needs to fix on most of the ARM platforms.

This patch makes timer related variables in gd_t available for
all ARM implementations.

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>

Edited commit message.
Signed-off-by: Wolfgang Denk <wd@denx.de>

I doubt the stack_setup() was defective before:
 we load the current location of _start and compare against destination
 of relocate_code(). If we are already there we shoud skip the
 relocation and jump over to clear_bss. Before the clear_bss was also skipped.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>

r8 is used for global_data and should therefore be left alone!

For C code the compiler flag --fixed-r8 does the job, but in assembler
we need to be aware of that fact.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>

In case we are still at relocation target address before relocation we
do not need to load the registers needed for relocation. We should
instead skip the whole relocation part and jump over to clear_bss
immediately.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>

This patch uses r1 as scratch register for copy_loop(). Therefore we do
not longer need r7 for the storage of relocate_code()'s 'addr_moni' (the
destination address of relocation).
Therefore r7 can be used later on for other purposes.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>