This patch adds support for the T3CORP board, based on the
AppliedMicro (APM) PPC460GT.

Signed-off-by: Stefan Roese <sr@denx.de>

Background Info:
Some PPC440/460 boards have caches enabled in the Boot/FLASH TLB (via
init.S) to speed up the boot process. In relocate_code (start.S) the
cache inhibit attribute for this TLB is set to disable cache. This is
needed for the CFI FLASH driver.

This patch now cleans this code up:
- CONFIG_SYS_TLB_FOR_BOOT_FLASH is defined to 0 (default TLB) if not
  defined in the top of this file. This way, we can remove an ugly
  #ifdef in this code.
- Replace complex "#if defined(CONFIG_440EP) || defined(CONFIG_GR)..."
  statement with "#if defined(CONFIG_440)".
- Remove unnecessary cache invalidate calls resulting in faster bootup.

Signed-off-by: Stefan Roese <sr@denx.de>

This patch adds some DDR(2) macros to all PPC4xx's equipped with
this IBM DDR1/2 controller.

Signed-off-by: Stefan Roese <sr@denx.de>

As described in item #10 of the SDRAM initialization (chapter 22.2.9
of the PPC460EX/EXr/GT users manual), RDSS may need to be adjusted. The
code for this is now factored out and executed for non-SPD based boards
as well.

Signed-off-by: Stefan Roese <sr@denx.de>

This patch makes it possible to overwrite the default auto-calibration
scan window (SDRAM_WRDTR.[WDTR], SDRAM_CLKTR.[CKTR] values) with
board specific values. The parameters of the weak default function are
corrected as well. This way we don't need the casts any more.

This feature will be used by an upcoming PPC460GT board port.

Signed-off-by: Stefan Roese <sr@denx.de>

By not defining CONFIG_SYS_PCI_MASTER_INIT and CONFIG_SYS_PCI_TARGET_INIT,
PCI support (host and adapter) will not be enabled. But it's still
possible to use the U-Boot PCI infrastructure for the PCIe ports.

This configuration option is needed for a new 460GT board, which uses
PCIe but has PCI disabled.

Signed-off-by: Stefan Roese <sr@denx.de>

This patch enables booting with option E on the PPC460EX/EXr/GT.
When booting with Option E, the PLL is in bypass, CPR0_PLLC[ENG]=0.
The Software Boot Configuration Procedure is needed to engage the
PLL and perform a chip reset.

Signed-off-by: Stefan Roese <sr@denx.de>

Update CHANGELOG

Signed-off-by: Wolfgang Denk <wd@denx.de>

This also uses the breadcrumb register as on MPC5200.

Signed-off-by: Michael Weiss <michael.weiss@ifm.com>
Signed-off-by: Detlev Zundel <dzu@denx.de>

r12 is used for accessing the GOT not r14. Fix this in the
comment.

Signed-off-by: Heiko Schocher <hs@denx.de>

We were missing 8641HPCN_36BIT and MPC8536DS_36BIT.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>

Fix following warnings:

$ ./MAKEALL EVB64260 P3G4 ZUMA
Configuring for EVB64260 board...
mpsc.c: In function 'mpsc_putchar_early':
mpsc.c:121: warning: dereferencing type-punned pointer will break strict-aliasing rules
mpsc.c:127: warning: dereferencing type-punned pointer will break strict-aliasing rules
...

Signed-off-by: Anatolij Gustschin <agust@denx.de>

ehci_submit_async() doesn't really zero out the QH transfer overlay (as the EHCI
specification suggests) which leads to the controller seeing the "token" field
as the previous call has left it, i.e.:
- if a timeout occured on the previous call (Active bit left as 1), controller
  incorrectly tries to complete a previous transaction on a newly programmed
  endpoint;
- if a halt occured on the previous call (Halted bit set to 1), controller just
  ignores the newly programmed TD(s) and the function then keeps returning error
  ad infinitum.

This turned out to be caused by the wrong orger of the arguments to the memset()
call in ehci_alloc(), so the allocated TDs weren't cleared either.

While at it, stop needlessly initializing the alternate next TD pointer in the
QH transfer overlay...

Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Acked-by: Remy Bohmer <linux@bohmer.net>

The console_buffer size is declared in common/main.c as
   -- char console_buffer[CONFIG_SYS_CBSIZE + 1];
so this extern definition is wrong.

Signed-off-by: Remy Bohmer <linux@bohmer.net>

- Also modified the code to use io accessors.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>

On P2020RDB eTSEC2 is connected to Vitesse VSC8221 PHY via SGMII.
Current TBI PHY settings for SGMII mode cause link problems on
this platform, link never comes up.

Fix this by making TBI PHY settings configurable and add a working
configuration for P2020RDB.

Signed-off-by: Felix Radensky <felix@embedded-sol.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Acked-by: Peter Tyser <ptyser@xes-inc.com>
Tested-by: Peter Tyser <ptyser@xes-inc.com>

Add a sort of batch mode to fw_setenv, allowing to set
multiple variables in one shot, without updating the flash after
each set as now. It is added the possibility to pass
a config file with a list of pairs <variable, value> to be set,
separated by a TAB character.

Signed-off-by: Stefano Babic <sbabic@denx.de>

This patch fixes following error:

zlib.c:31:27: error: asm/unaligned.h: No such file or directory

Suggested-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Andreas Biemann <biessmann@corscience.de>

When building some avr32 boards out of tree (e.g. O=..) the linker script could
not be found. This patch references the linker script in source tree.

Signed-off-by: Andreas Bießmann <biessmann@corscience.de>

Due to a hardware bug mentioned in latest AP7000 datasheet errata
(revision M from 09.09) branch folding is unreliable.
This patch disables CPUCR.FE bitfield as stated in datasheet.

Signed-off-by: Andreas Biemann <biessmann@corscience.de>

AVR32 case was missing in cmd_bdinfo, resulting in compiler warning
(bd->bi_baudrate declared unsigned int at AVR32, but printf used %d)

At the same time slightly reordered #if #elif #endif to make ARM one
of the cases and not an extra case surrounding all others

Signed-off-by: Reinhard Meyer <info@emk-elektronik.de>
Tested-by: Andreas Bießmann <biessmann@corscience.de>

Currently the U-Boot address ranges for AVR32 boards are
printed like this:
"U-Boot code: (null) -> 0001183c  data: 000188e8 -> 0004e9b0"
This patch fixes this to print:
"U-Boot code: 00000000 -> 0001183c  data: 000188f8 -> 0004e9c0"

Signed-off-by: Reinhard Meyer <info@emk-elektronik.de>

Previously, standalone applications were compiled with gcc flags that
produced relocatable executables on the PowerPC architecture (eg with
the -mrelocatable and -fPIC flags).  There's no reason for these
applications to be fully relocatable at this time since no relocation
fixups are performed on standalone applications.

Additionally, removing the gcc relocation flags results in the entry
point of applications residing at the base of the image.  When
a standalone application was relocatable, the entry point was generally
located at an offset into the image which was confusing and prone to
errors.

This change moves the entry point of PowerPC standalone applications
from 0x40004 (usually) to 0x40000.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>

I use this for testing, and I think this might be useful in the
future.

Signed-off-by: Anton Vorontsov <avorontsov@mvista.com>

For the following hwconfig string:

  key1:subkey1=value1,subkey2=value2;key2:value3

The subkey2 cannot be extracted correctly. The parsing code looks
for comma as a stopch, but there may be two kind of stop characters:
a comma and a semicolon.

Currently the code would return "value2;key2:value3", while just
"value2" is the correct answer.

This patch fixes the issue by making the code aware of multiple
stop characters.

For old U-Boots, the issue can be workarounded by placing a comma
before a semicolon, i.e.:

  hwconfig=key1:subkey1=value1,subkey2=value2,;key2:value3

Reported-by: York Sun <yorksun@freescale.com>
Signed-off-by: Anton Vorontsov <avorontsov@mvista.com>

ISO C does not allow extra ';' outside of a function

Signed-off-by: Wolfgang Denk <wd@denx.de>

The console_buffer size is declared in common/main.c as
   -- char console_buffer[CONFIG_SYS_CBSIZE + 1];
so this extern definition is wrong.

Signed-off-by: Remy Bohmer <linux@bohmer.net>

- Also modified the code to use io accessors.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>

On P2020RDB eTSEC2 is connected to Vitesse VSC8221 PHY via SGMII.
Current TBI PHY settings for SGMII mode cause link problems on
this platform, link never comes up.

Fix this by making TBI PHY settings configurable and add a working
configuration for P2020RDB.

Signed-off-by: Felix Radensky <felix@embedded-sol.com>
Acked-by: Andy Fleming <afleming@freescale.com>

Use a slighly larger value of CLK_CTRL for DDR at 667MHz
which fixes random crashes while linux booting.

Applicable for both NAND and NOR boot.

Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>

Because the variable was getting defined twice.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>

Commit 460c2ce3 "MPC5200: workaround data corruption for unaligned
local bus accesses" fixed the problem for MPC5200 only, but MPC512x is
affected as well, so apply the same fix here, too.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>

This add support cpu reset by trigger_address_error function.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>