ARM: at91: sama5d2: configure the L2 cache memory

The SAMA5D2 has a second internal SRAM that can be reassigned as a L2
cache memory.
Make sure it is configured as a L2 cache memory when booting from a SPL
image.

Based on the commit b5ea95ef2b5b from the at91bootstrap repository.

Signed-off-by: Samuel Mescoff <samuel.mescoff@mobile-devices.fr>
Reviewed-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>

arch/arm/mach-at91/atmel_sfr.c

@@ -19,3 +19,10 @@ void redirect_int_from_saic_to_aic(void)
 		writel((key32 | ATMEL_SFR_AICREDIR_NSAIC), &sfr->aicredir);
 	}
 }
+
+void configure_2nd_sram_as_l2_cache(void)
+{
+	struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
+
+	writel(1, &sfr->l2cc_hramc);
+}

arch/arm/mach-at91/include/mach/at91_common.h

@@ -34,5 +34,6 @@ void at91_spl_board_init(void);
 void at91_disable_wdt(void);
 void matrix_init(void);
 void redirect_int_from_saic_to_aic(void);
+void configure_2nd_sram_as_l2_cache(void);
 
 #endif /* AT91_COMMON_H */

arch/arm/mach-at91/include/mach/sama5_sfr.h

@@ -25,6 +25,7 @@ struct atmel_sfr {
 	u32 sn0;		/* 0x4c */
 	u32 sn1;		/* 0x50 */
 	u32 aicredir;	/* 0x54 */
+	u32 l2cc_hramc;	/* 0x58 */
 };
 
 /* Bit field in DDRCFG */

arch/arm/mach-at91/spl_atmel.c

@@ -79,6 +79,10 @@ void board_init_f(ulong dummy)
 {
 	switch_to_main_crystal_osc();
 
+#ifdef CONFIG_SAMA5D2
+	configure_2nd_sram_as_l2_cache();
+#endif
+
 	/* disable watchdog */
 	at91_disable_wdt();