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Commit 0d8c3a20 authored by Andy Fleming's avatar Andy Fleming Committed by Andrew Fleming-AFLEMING
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Support 1G size on 8548


e500v2 and newer cores support 1G page sizes.

Signed-off-by: default avatarEd Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
parent 45cef612
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...@@ -995,17 +995,24 @@ setup_laws_and_tlbs(unsigned int memsize) ...@@ -995,17 +995,24 @@ setup_laws_and_tlbs(unsigned int memsize)
break; break;
case 256: case 256:
case 512: case 512:
tlb_size = BOOKE_PAGESZ_256M;
break;
case 1024: case 1024:
case 2048: case 2048:
tlb_size = BOOKE_PAGESZ_256M; if (PVR_VER(get_pvr()) > PVR_VER(PVR_85xx))
tlb_size = BOOKE_PAGESZ_1G;
else
tlb_size = BOOKE_PAGESZ_256M;
break; break;
default: default:
puts("DDR: only 16M,32M,64M,128M,256M,512M,1G and 2G are supported.\n"); puts("DDR: only 16M,32M,64M,128M,256M,512M,1G and 2G are supported.\n");
/* /*
* The memory was not able to be mapped. * The memory was not able to be mapped.
* Default to a small size.
*/ */
return 0; tlb_size = BOOKE_PAGESZ_64M;
memsize=64;
break; break;
} }
......
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