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Sricharan R authored
The sys_clk on the dra evm board is 20MHZ. Changing the configuration for the same. And also moving V_SCLK, V_OSCK defines to arch/clock.h for OMAP4+ boards. Signed-off-by:
Sricharan R <r.sricharan@ti.com> Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Sricharan R authoredThe sys_clk on the dra evm board is 20MHZ. Changing the configuration for the same. And also moving V_SCLK, V_OSCK defines to arch/clock.h for OMAP4+ boards. Signed-off-by:
