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Commit f9b814a8 authored by Sricharan R's avatar Sricharan R Committed by Tom Rini
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ARM: DRA7xx: Correct the SYS_CLK to 20MHZ 


The sys_clk on the dra evm board is 20MHZ.
Changing the configuration for the same.
And also moving V_SCLK, V_OSCK defines to
arch/clock.h for OMAP4+ boards.

Signed-off-by: default avatarSricharan R <r.sricharan@ti.com>
Signed-off-by: default avatarLokesh Vutla <lokeshvutla@ti.com>
parent 378bd1fb
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