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Timur Tabi authored
SerDes PLL bandwidth default setting is incorrect when no lanes are configured as PCI Express. Signed-off-by:
Timur Tabi <timur@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
Timur Tabi authoredSerDes PLL bandwidth default setting is incorrect when no lanes are configured as PCI Express. Signed-off-by:
