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Commit da30b9fd authored by Timur Tabi's avatar Timur Tabi Committed by Kumar Gala
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powerpc/85xx: Implement work-around for P4080 erratum SERDES-A005 


SerDes PLL bandwidth default setting is incorrect when no lanes are
configured as PCI Express.

Signed-off-by: default avatarTimur Tabi <timur@freescale.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent 82c9dfdc
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