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    64852d09
    ppc4xx/NAND_SPL: Consolidate 405 and 440 NAND booting code in start.S · 64852d09
    Stefan Roese authored
    
    This patch consolidates the 405 and 440 parts of the NAND booting code
    selected via CONFIG_NAND_SPL. Now common code is used to initialize the
    SDRAM by calling initdram() and to "copy/relocate" to SDRAM/OCM/etc.
    Only *after* running from this location, nand_boot() is called.
    
    Please note that the initsdram() call is now moved from nand_boot.c
    to start.S. I experienced problems with some boards like Kilauea
    (405EX), which don't have internal SRAM (OCM) and relocation needs to
    be done to SDRAM before the NAND controller can get accessed. When
    initdram() is called later on in nand_boot(), this can lead to problems
    with variables in the bss sections like nand_ecc_pos[].
    
    Signed-off-by: default avatarStefan Roese <sr@denx.de>
    Acked-by: default avatarScott Wood <scottwood@freescale.com>
    64852d09
    History
    ppc4xx/NAND_SPL: Consolidate 405 and 440 NAND booting code in start.S
    Stefan Roese authored
    
    This patch consolidates the 405 and 440 parts of the NAND booting code
    selected via CONFIG_NAND_SPL. Now common code is used to initialize the
    SDRAM by calling initdram() and to "copy/relocate" to SDRAM/OCM/etc.
    Only *after* running from this location, nand_boot() is called.
    
    Please note that the initsdram() call is now moved from nand_boot.c
    to start.S. I experienced problems with some boards like Kilauea
    (405EX), which don't have internal SRAM (OCM) and relocation needs to
    be done to SDRAM before the NAND controller can get accessed. When
    initdram() is called later on in nand_boot(), this can lead to problems
    with variables in the bss sections like nand_ecc_pos[].
    
    Signed-off-by: default avatarStefan Roese <sr@denx.de>
    Acked-by: default avatarScott Wood <scottwood@freescale.com>