4xx_enet.c

		mode_reg |= EMAC_MR1_OBCI_83;
	else if (opbfreq <= 100)
		mode_reg |= EMAC_MR1_OBCI_100;
	else
		mode_reg |= EMAC_MR1_OBCI_GT100;

	out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg);
#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */

#if defined(CONFIG_GPCS_PHY_ADDR) || defined(CONFIG_GPCS_PHY1_ADDR) || \
    defined(CONFIG_GPCS_PHY2_ADDR) || defined(CONFIG_GPCS_PHY3_ADDR)
	if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) {
		/*
		 * In SGMII mode, GPCS access is needed for
		 * communication with the internal SGMII SerDes.
		 */
		switch (devnum) {
#if defined(CONFIG_GPCS_PHY_ADDR)
		case 0:
			reg = CONFIG_GPCS_PHY_ADDR;
			break;
#endif
#if defined(CONFIG_GPCS_PHY1_ADDR)
		case 1:
			reg = CONFIG_GPCS_PHY1_ADDR;
			break;
#endif
#if defined(CONFIG_GPCS_PHY2_ADDR)
		case 2:
			reg = CONFIG_GPCS_PHY2_ADDR;
			break;
#endif
#if defined(CONFIG_GPCS_PHY3_ADDR)
		case 3:
			reg = CONFIG_GPCS_PHY3_ADDR;
			break;
#endif
		}

		mode_reg = in_be32((void *)EMAC0_MR1 + hw_p->hw_addr);
		mode_reg |= EMAC_MR1_MF_1000GPCS | EMAC_MR1_IPPA_SET(reg);
		out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg);

		/* Configure GPCS interface to recommended setting for SGMII */
		miiphy_reset(dev->name, reg);
		miiphy_write(dev->name, reg, 0x04, 0x8120); /* AsymPause, FDX */
		miiphy_write(dev->name, reg, 0x07, 0x2801); /* msg_pg, toggle */
		miiphy_write(dev->name, reg, 0x00, 0x0140); /* 1Gbps, FDX     */
	}
#endif /* defined(CONFIG_GPCS_PHY_ADDR) */

	/* wait for PHY to complete auto negotiation */
	reg_short = 0;
	switch (devnum) {
	case 0:
		reg = CONFIG_PHY_ADDR;
		break;
#if defined (CONFIG_PHY1_ADDR)
	case 1:
		reg = CONFIG_PHY1_ADDR;
		break;
#endif
#if defined (CONFIG_PHY2_ADDR)
	case 2:
		reg = CONFIG_PHY2_ADDR;
		break;
#endif
#if defined (CONFIG_PHY3_ADDR)
	case 3:
		reg = CONFIG_PHY3_ADDR;
		break;
#endif
	default:
		reg = CONFIG_PHY_ADDR;
		break;
	}

	bis->bi_phynum[devnum] = reg;

	if (reg == CONFIG_FIXED_PHY)
		goto get_speed;

#if defined(CONFIG_PHY_RESET)
	/*
	 * Reset the phy, only if its the first time through
	 * otherwise, just check the speeds & feeds
	 */
	if (hw_p->first_init == 0) {
#if defined(CONFIG_M88E1111_PHY)
		miiphy_write (dev->name, reg, 0x14, 0x0ce3);
		miiphy_write (dev->name, reg, 0x18, 0x4101);
		miiphy_write (dev->name, reg, 0x09, 0x0e00);
		miiphy_write (dev->name, reg, 0x04, 0x01e1);
#if defined(CONFIG_M88E1111_DISABLE_FIBER)
		miiphy_read(dev->name, reg, 0x1b, &reg_short);
		reg_short |= 0x8000;
		miiphy_write(dev->name, reg, 0x1b, reg_short);
#endif
#endif
#if defined(CONFIG_M88E1112_PHY)
		if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) {
			/*
			 * Marvell 88E1112 PHY needs to have the SGMII MAC
			 * interace (page 2) properly configured to
			 * communicate with the 460EX/GT GPCS interface.
			 */

			/* Set access to Page 2 */
			miiphy_write(dev->name, reg, 0x16, 0x0002);

			miiphy_write(dev->name, reg, 0x00, 0x0040); /* 1Gbps */
			miiphy_read(dev->name, reg, 0x1a, &reg_short);
			reg_short |= 0x8000; /* bypass Auto-Negotiation */
			miiphy_write(dev->name, reg, 0x1a, reg_short);
			miiphy_reset(dev->name, reg); /* reset MAC interface */

			/* Reset access to Page 0 */
			miiphy_write(dev->name, reg, 0x16, 0x0000);
		}
#endif /* defined(CONFIG_M88E1112_PHY) */
		miiphy_reset (dev->name, reg);

#if defined(CONFIG_440GX) || \
    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
    defined(CONFIG_405EX)

#if defined(CONFIG_CIS8201_PHY)
		/*
		 * Cicada 8201 PHY needs to have an extended register whacked
		 * for RGMII mode.
		 */
		if (((devnum == 2) || (devnum == 3)) && (4 == ethgroup)) {
#if defined(CONFIG_CIS8201_SHORT_ETCH)
			miiphy_write (dev->name, reg, 23, 0x1300);
#else
			miiphy_write (dev->name, reg, 23, 0x1000);
#endif
			/*
			 * Vitesse VSC8201/Cicada CIS8201 errata:
			 * Interoperability problem with Intel 82547EI phys
			 * This work around (provided by Vitesse) changes
			 * the default timer convergence from 8ms to 12ms
			 */
			miiphy_write (dev->name, reg, 0x1f, 0x2a30);
			miiphy_write (dev->name, reg, 0x08, 0x0200);
			miiphy_write (dev->name, reg, 0x1f, 0x52b5);
			miiphy_write (dev->name, reg, 0x02, 0x0004);
			miiphy_write (dev->name, reg, 0x01, 0x0671);
			miiphy_write (dev->name, reg, 0x00, 0x8fae);
			miiphy_write (dev->name, reg, 0x1f, 0x2a30);
			miiphy_write (dev->name, reg, 0x08, 0x0000);
			miiphy_write (dev->name, reg, 0x1f, 0x0000);
			/* end Vitesse/Cicada errata */
		}
#endif /* defined(CONFIG_CIS8201_PHY) */

#if defined(CONFIG_ET1011C_PHY)
		/*
		 * Agere ET1011c PHY needs to have an extended register whacked
		 * for RGMII mode.
		 */
		if (((devnum == 2) || (devnum ==3)) && (4 == ethgroup)) {
			miiphy_read (dev->name, reg, 0x16, &reg_short);
			reg_short &= ~(0x7);
			reg_short |= 0x6;	/* RGMII DLL Delay*/
			miiphy_write (dev->name, reg, 0x16, reg_short);

			miiphy_read (dev->name, reg, 0x17, &reg_short);
			reg_short &= ~(0x40);
			miiphy_write (dev->name, reg, 0x17, reg_short);

			miiphy_write(dev->name, reg, 0x1c, 0x74f0);
		}
#endif /* defined(CONFIG_ET1011C_PHY) */

#endif /* defined(CONFIG_440GX) ... */
		/* Start/Restart autonegotiation */
		phy_setup_aneg (dev->name, reg);
		udelay (1000);
	}
#endif /* defined(CONFIG_PHY_RESET) */

	miiphy_read (dev->name, reg, MII_BMSR, &reg_short);

	/*
	 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
	 */
	if ((reg_short & BMSR_ANEGCAPABLE)
	    && !(reg_short & BMSR_ANEGCOMPLETE)) {
		puts ("Waiting for PHY auto negotiation to complete");
		i = 0;
		while (!(reg_short & BMSR_ANEGCOMPLETE)) {
			/*
			 * Timeout reached ?
			 */
			if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
				puts (" TIMEOUT !\n");
				break;
			}

			if ((i++ % 1000) == 0) {
				putc ('.');
			}
			udelay (1000);	/* 1 ms */
			miiphy_read (dev->name, reg, MII_BMSR, &reg_short);
		}
		puts (" done\n");
		udelay (500000);	/* another 500 ms (results in faster booting) */
	}

get_speed:
	if (reg == CONFIG_FIXED_PHY) {
		for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) {
			if (devnum == fixed_phy_port[i].devnum) {
				speed = fixed_phy_port[i].speed;
				duplex = fixed_phy_port[i].duplex;
				break;
			}
		}

		if (i == ARRAY_SIZE(fixed_phy_port)) {
			printf("ERROR: PHY (%s) not configured correctly!\n",
				dev->name);
			return -1;
		}
	} else {
		speed = miiphy_speed(dev->name, reg);
		duplex = miiphy_duplex(dev->name, reg);
	}

	if (hw_p->print_speed) {
		hw_p->print_speed = 0;
		printf ("ENET Speed is %d Mbps - %s duplex connection (EMAC%d)\n",
			(int) speed, (duplex == HALF) ? "HALF" : "FULL",
			hw_p->devnum);
	}

#if defined(CONFIG_440) && \
    !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
    !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
    !defined(CONFIG_460EX) && !defined(CONFIG_460GT)
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
	mfsdr(SDR0_MFR, reg);
	if (speed == 100) {
		reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
	} else {
		reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
	}
	mtsdr(SDR0_MFR, reg);
#endif

	/* Set ZMII/RGMII speed according to the phy link speed */
	reg = in_be32((void *)ZMII0_SSR);
	if ( (speed == 100) || (speed == 1000) )
		out_be32((void *)ZMII0_SSR, reg | (ZMII0_SSR_SP << ZMII0_SSR_V (devnum)));
	else
		out_be32((void *)ZMII0_SSR, reg & (~(ZMII0_SSR_SP << ZMII0_SSR_V (devnum))));

	if ((devnum == 2) || (devnum == 3)) {
		if (speed == 1000)
			reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
		else if (speed == 100)
			reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
		else if (speed == 10)
			reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
		else {
			printf("Error in RGMII Speed\n");
			return -1;
		}
		out_be32((void *)RGMII_SSR, reg);
	}
#endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */

#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
    defined(CONFIG_405EX)
	if (devnum >= 2)
		rgmii_channel = devnum - 2;
	else
		rgmii_channel = devnum;

	if (speed == 1000)
		reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V(rgmii_channel));
	else if (speed == 100)
		reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V(rgmii_channel));
	else if (speed == 10)
		reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V(rgmii_channel));
	else {
		printf("Error in RGMII Speed\n");
		return -1;
	}
	out_be32((void *)RGMII_SSR, reg);
#if defined(CONFIG_460GT)
	if ((devnum == 2) || (devnum == 3))
		out_be32((void *)RGMII_SSR + RGMII1_BASE_OFFSET, reg);
#endif
#endif

	/* set the Mal configuration reg */
#if defined(CONFIG_440GX) || \
    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
    defined(CONFIG_405EX)
	mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
	       MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
#else
	mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
	/* Errata 1.12: MAL_1 -- Disable MAL bursting */
	if (get_pvr() == PVR_440GP_RB) {
		mtdcr (MAL0_CFG, mfdcr(MAL0_CFG) & ~MAL_CR_PLBB);
	}
#endif

	/*
	 * Malloc MAL buffer desciptors, make sure they are
	 * aligned on cache line boundary size
	 * (401/403/IOP480 = 16, 405 = 32)
	 * and doesn't cross cache block boundaries.
	 */
	if (hw_p->first_init == 0) {
		debug("*** Allocating descriptor memory ***\n");

		bd_cached = (u32)malloc_aligned(MAL_ALLOC_SIZE, 4096);
		if (!bd_cached) {
			printf("%s: Error allocating MAL descriptor buffers!\n", __func__);
			return -1;
		}

#ifdef CONFIG_4xx_DCACHE
		flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE);
		if (!last_used_ea)
#if defined(CONFIG_SYS_MEM_TOP_HIDE)
			bd_uncached = bis->bi_memsize + CONFIG_SYS_MEM_TOP_HIDE;
#else
			bd_uncached = bis->bi_memsize;
#endif
		else
			bd_uncached = last_used_ea + MAL_ALLOC_SIZE;

		last_used_ea = bd_uncached;
		program_tlb(bd_cached, bd_uncached, MAL_ALLOC_SIZE,
			    TLB_WORD2_I_ENABLE);
#else
		bd_uncached = bd_cached;
#endif
		hw_p->tx_phys = bd_cached;
		hw_p->rx_phys = bd_cached + MAL_TX_DESC_SIZE;
		hw_p->tx = (mal_desc_t *)(bd_uncached);
		hw_p->rx = (mal_desc_t *)(bd_uncached + MAL_TX_DESC_SIZE);
		debug("hw_p->tx=%p, hw_p->rx=%p\n", hw_p->tx, hw_p->rx);
	}

	for (i = 0; i < NUM_TX_BUFF; i++) {
		hw_p->tx[i].ctrl = 0;
		hw_p->tx[i].data_len = 0;
		if (hw_p->first_init == 0)
			hw_p->txbuf_ptr = malloc_aligned(MAL_ALLOC_SIZE,
							 L1_CACHE_BYTES);
		hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
		if ((NUM_TX_BUFF - 1) == i)
			hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
		hw_p->tx_run[i] = -1;
		debug("TX_BUFF %d @ 0x%08x\n", i, (u32)hw_p->tx[i].data_ptr);
	}

	for (i = 0; i < NUM_RX_BUFF; i++) {
		hw_p->rx[i].ctrl = 0;
		hw_p->rx[i].data_len = 0;
		hw_p->rx[i].data_ptr = (char *)NetRxPackets[i];
		if ((NUM_RX_BUFF - 1) == i)
			hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
		hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
		hw_p->rx_ready[i] = -1;
		debug("RX_BUFF %d @ 0x%08x\n", i, (u32)hw_p->rx[i].data_ptr);
	}

	reg = 0x00000000;

	reg |= dev->enetaddr[0];	/* set high address */
	reg = reg << 8;
	reg |= dev->enetaddr[1];

	out_be32((void *)EMAC0_IAH + hw_p->hw_addr, reg);

	reg = 0x00000000;
	reg |= dev->enetaddr[2];	/* set low address  */
	reg = reg << 8;
	reg |= dev->enetaddr[3];
	reg = reg << 8;
	reg |= dev->enetaddr[4];
	reg = reg << 8;
	reg |= dev->enetaddr[5];

	out_be32((void *)EMAC0_IAL + hw_p->hw_addr, reg);

	switch (devnum) {
	case 1:
		/* setup MAL tx & rx channel pointers */
#if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
		mtdcr (MAL0_TXCTP2R, hw_p->tx_phys);
#else
		mtdcr (MAL0_TXCTP1R, hw_p->tx_phys);
#endif
#if defined(CONFIG_440)
		mtdcr (MAL0_TXBADDR, 0x0);
		mtdcr (MAL0_RXBADDR, 0x0);
#endif

#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
		mtdcr (MAL0_RXCTP8R, hw_p->rx_phys);
		/* set RX buffer size */
		mtdcr (MAL0_RCBS8, ENET_MAX_MTU_ALIGNED / 16);
#else
		mtdcr (MAL0_RXCTP1R, hw_p->rx_phys);
		/* set RX buffer size */
		mtdcr (MAL0_RCBS1, ENET_MAX_MTU_ALIGNED / 16);
#endif
		break;
#if defined (CONFIG_440GX)
	case 2:
		/* setup MAL tx & rx channel pointers */
		mtdcr (MAL0_TXBADDR, 0x0);
		mtdcr (MAL0_RXBADDR, 0x0);
		mtdcr (MAL0_TXCTP2R, hw_p->tx_phys);
		mtdcr (MAL0_RXCTP2R, hw_p->rx_phys);
		/* set RX buffer size */
		mtdcr (MAL0_RCBS2, ENET_MAX_MTU_ALIGNED / 16);
		break;
	case 3:
		/* setup MAL tx & rx channel pointers */
		mtdcr (MAL0_TXBADDR, 0x0);
		mtdcr (MAL0_TXCTP3R, hw_p->tx_phys);
		mtdcr (MAL0_RXBADDR, 0x0);
		mtdcr (MAL0_RXCTP3R, hw_p->rx_phys);
		/* set RX buffer size */
		mtdcr (MAL0_RCBS3, ENET_MAX_MTU_ALIGNED / 16);
		break;
#endif /* CONFIG_440GX */
#if defined (CONFIG_460GT)
	case 2:
		/* setup MAL tx & rx channel pointers */
		mtdcr (MAL0_TXBADDR, 0x0);
		mtdcr (MAL0_RXBADDR, 0x0);
		mtdcr (MAL0_TXCTP2R, hw_p->tx_phys);
		mtdcr (MAL0_RXCTP16R, hw_p->rx_phys);
		/* set RX buffer size */
		mtdcr (MAL0_RCBS16, ENET_MAX_MTU_ALIGNED / 16);
		break;
	case 3:
		/* setup MAL tx & rx channel pointers */
		mtdcr (MAL0_TXBADDR, 0x0);
		mtdcr (MAL0_RXBADDR, 0x0);
		mtdcr (MAL0_TXCTP3R, hw_p->tx_phys);
		mtdcr (MAL0_RXCTP24R, hw_p->rx_phys);
		/* set RX buffer size */
		mtdcr (MAL0_RCBS24, ENET_MAX_MTU_ALIGNED / 16);
		break;
#endif /* CONFIG_460GT */
	case 0:
	default:
		/* setup MAL tx & rx channel pointers */
#if defined(CONFIG_440)
		mtdcr (MAL0_TXBADDR, 0x0);
		mtdcr (MAL0_RXBADDR, 0x0);
#endif
		mtdcr (MAL0_TXCTP0R, hw_p->tx_phys);
		mtdcr (MAL0_RXCTP0R, hw_p->rx_phys);
		/* set RX buffer size */
		mtdcr (MAL0_RCBS0, ENET_MAX_MTU_ALIGNED / 16);
		break;
	}

	/* Enable MAL transmit and receive channels */
#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
	mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
#else
	mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> hw_p->devnum));
#endif
	mtdcr (MAL0_RXCASR, (MAL_TXRX_CASR >> hw_p->devnum));

	/* set transmit enable & receive enable */
	out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_TXE | EMAC_MR0_RXE);

	mode_reg = in_be32((void *)EMAC0_MR1 + hw_p->hw_addr);

	/* set rx-/tx-fifo size */
	mode_reg = (mode_reg & ~EMAC_MR1_FIFO_MASK) | EMAC_MR1_FIFO_SIZE;

	/* set speed */
	if (speed == _1000BASET) {
#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
		unsigned long pfc1;

		mfsdr (SDR0_PFC1, pfc1);
		pfc1 |= SDR0_PFC1_EM_1000;
		mtsdr (SDR0_PFC1, pfc1);
#endif
		mode_reg = mode_reg | EMAC_MR1_MF_1000MBPS | EMAC_MR1_IST;
	} else if (speed == _100BASET)
		mode_reg = mode_reg | EMAC_MR1_MF_100MBPS | EMAC_MR1_IST;
	else
		mode_reg = mode_reg & ~0x00C00000;	/* 10 MBPS */
	if (duplex == FULL)
		mode_reg = mode_reg | 0x80000000 | EMAC_MR1_IST;

	out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg);

	/* Enable broadcast and indvidual address */
	/* TBS: enabling runts as some misbehaved nics will send runts */
	out_be32((void *)EMAC0_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);

	/* we probably need to set the tx mode1 reg? maybe at tx time */

	/* set transmit request threshold register */
	out_be32((void *)EMAC0_TRTR + hw_p->hw_addr, 0x18000000);	/* 256 byte threshold */

	/* set receive	low/high water mark register */
#if defined(CONFIG_440)
	/* 440s has a 64 byte burst length */
	out_be32((void *)EMAC0_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
#else
	/* 405s have a 16 byte burst length */
	out_be32((void *)EMAC0_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
#endif /* defined(CONFIG_440) */
	out_be32((void *)EMAC0_TMR1 + hw_p->hw_addr, 0xf8640000);

	/* Set fifo limit entry in tx mode 0 */
	out_be32((void *)EMAC0_TMR0 + hw_p->hw_addr, 0x00000003);
	/* Frame gap set */
	out_be32((void *)EMAC0_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);

	/* Set EMAC IER */
	hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE;
	if (speed == _100BASET)
		hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;

	out_be32((void *)EMAC0_ISR + hw_p->hw_addr, 0xffffffff);	/* clear pending interrupts */
	out_be32((void *)EMAC0_IER + hw_p->hw_addr, hw_p->emac_ier);

	if (hw_p->first_init == 0) {
		/*
		 * Connect interrupt service routines
		 */
		irq_install_handler(ETH_IRQ_NUM(hw_p->devnum),
				    (interrupt_handler_t *) enetInt, dev);
	}

	mtmsr (msr);		/* enable interrupts again */

	hw_p->bis = bis;
	hw_p->first_init = 1;

	return 0;
}


static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
			      int len)
{
	struct enet_frame *ef_ptr;
	ulong time_start, time_now;
	unsigned long temp_txm0;
	EMAC_4XX_HW_PST hw_p = dev->priv;

	ef_ptr = (struct enet_frame *) ptr;

	/*-----------------------------------------------------------------------+
	 *  Copy in our address into the frame.
	 *-----------------------------------------------------------------------*/
	(void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);

	/*-----------------------------------------------------------------------+
	 * If frame is too long or too short, modify length.
	 *-----------------------------------------------------------------------*/
	/* TBS: where does the fragment go???? */
	if (len > ENET_MAX_MTU)
		len = ENET_MAX_MTU;

	/*   memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
	memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
	flush_dcache_range((u32)hw_p->txbuf_ptr, (u32)hw_p->txbuf_ptr + len);

	/*-----------------------------------------------------------------------+
	 * set TX Buffer busy, and send it
	 *-----------------------------------------------------------------------*/
	hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
					EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
		~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
	if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
		hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;

	hw_p->tx[hw_p->tx_slot].data_len = (short) len;
	hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;

	sync();

	out_be32((void *)EMAC0_TMR0 + hw_p->hw_addr,
		 in_be32((void *)EMAC0_TMR0 + hw_p->hw_addr) | EMAC_TMR0_GNP0);
#ifdef INFO_4XX_ENET
	hw_p->stats.pkts_tx++;
#endif

	/*-----------------------------------------------------------------------+
	 * poll unitl the packet is sent and then make sure it is OK
	 *-----------------------------------------------------------------------*/
	time_start = get_timer (0);
	while (1) {
		temp_txm0 = in_be32((void *)EMAC0_TMR0 + hw_p->hw_addr);
		/* loop until either TINT turns on or 3 seconds elapse */
		if ((temp_txm0 & EMAC_TMR0_GNP0) != 0) {
			/* transmit is done, so now check for errors
			 * If there is an error, an interrupt should
			 * happen when we return
			 */
			time_now = get_timer (0);
			if ((time_now - time_start) > 3000) {
				return (-1);
			}
		} else {
			return (len);
		}
	}
}

int enetInt (struct eth_device *dev)
{
	int serviced;
	int rc = -1;		/* default to not us */
	u32 mal_isr;
	u32 emac_isr = 0;
	u32 mal_eob;
	u32 uic_mal;
	u32 uic_mal_err;
	u32 uic_emac;
	u32 uic_emac_b;
	EMAC_4XX_HW_PST hw_p;

	/*
	 * Because the mal is generic, we need to get the current
	 * eth device
	 */
	dev = eth_get_dev();

	hw_p = dev->priv;

	/* enter loop that stays in interrupt code until nothing to service */
	do {
		serviced = 0;

		uic_mal = mfdcr(UIC_BASE_MAL + UIC_MSR);
		uic_mal_err = mfdcr(UIC_BASE_MAL_ERR + UIC_MSR);
		uic_emac = mfdcr(UIC_BASE_EMAC + UIC_MSR);
		uic_emac_b = mfdcr(UIC_BASE_EMAC_B + UIC_MSR);

		if (!(uic_mal & (UIC_MAL_RXEOB | UIC_MAL_TXEOB))
		    && !(uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE))
		    && !(uic_emac & UIC_ETHx) && !(uic_emac_b & UIC_ETHxB)) {
			/* not for us */
			return (rc);
		}

		/* get and clear controller status interrupts */
		/* look at MAL and EMAC error interrupts */
		if (uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)) {
			/* we have a MAL error interrupt */
			mal_isr = mfdcr(MAL0_ESR);
			mal_err(dev, mal_isr, uic_mal_err,
				 MAL_UIC_DEF, MAL_UIC_ERR);

			/* clear MAL error interrupt status bits */
			mtdcr(UIC_BASE_MAL_ERR + UIC_SR,
			      UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE);

			return -1;
		}

		/* look for EMAC errors */
		if ((uic_emac & UIC_ETHx) || (uic_emac_b & UIC_ETHxB)) {
			emac_isr = in_be32((void *)EMAC0_ISR + hw_p->hw_addr);
			emac_err(dev, emac_isr);

			/* clear EMAC error interrupt status bits */
			mtdcr(UIC_BASE_EMAC + UIC_SR, UIC_ETHx);
			mtdcr(UIC_BASE_EMAC_B + UIC_SR, UIC_ETHxB);

			return -1;
		}

		/* handle MAX TX EOB interrupt from a tx */
		if (uic_mal & UIC_MAL_TXEOB) {
			/* clear MAL interrupt status bits */
			mal_eob = mfdcr(MAL0_TXEOBISR);
			mtdcr(MAL0_TXEOBISR, mal_eob);
			mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_TXEOB);

			/* indicate that we serviced an interrupt */
			serviced = 1;
			rc = 0;
		}

		/* handle MAL RX EOB interrupt from a receive */
		/* check for EOB on valid channels	     */
		if (uic_mal & UIC_MAL_RXEOB) {
			mal_eob = mfdcr(MAL0_RXEOBISR);
			if (mal_eob &
			    (0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL))) {
				/* push packet to upper layer */
				enet_rcv(dev, emac_isr);

				/* clear MAL interrupt status bits */
				mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_RXEOB);

				/* indicate that we serviced an interrupt */
				serviced = 1;
				rc = 0;
			}
		}
#if defined(CONFIG_405EZ)
		/*
		 * On 405EZ the RX-/TX-interrupts are coalesced into
		 * one IRQ bit in the UIC. We need to acknowledge the
		 * RX-/TX-interrupts in the SDR0_ICINTSTAT reg as well.
		 */
		mtsdr(SDR0_ICINTSTAT,
		      SDR_ICRX_STAT | SDR_ICTX0_STAT | SDR_ICTX1_STAT);
#endif  /* defined(CONFIG_405EZ) */
	} while (serviced);

	return (rc);
}

/*-----------------------------------------------------------------------------+
 *  MAL Error Routine
 *-----------------------------------------------------------------------------*/
static void mal_err (struct eth_device *dev, unsigned long isr,
		     unsigned long uic, unsigned long maldef,
		     unsigned long mal_errr)
{
	EMAC_4XX_HW_PST hw_p = dev->priv;

	mtdcr (MAL0_ESR, isr);	/* clear interrupt */

	/* clear DE interrupt */
	mtdcr (MAL0_TXDEIR, 0xC0000000);
	mtdcr (MAL0_RXDEIR, 0x80000000);

#ifdef INFO_4XX_ENET
	printf ("\nMAL error occured.... ISR = %lx UIC = = %lx	MAL_DEF = %lx  MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
#endif

	eth_init (hw_p->bis);	/* start again... */
}

/*-----------------------------------------------------------------------------+
 *  EMAC Error Routine
 *-----------------------------------------------------------------------------*/
static void emac_err (struct eth_device *dev, unsigned long isr)
{
	EMAC_4XX_HW_PST hw_p = dev->priv;

	printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
	out_be32((void *)EMAC0_ISR + hw_p->hw_addr, isr);
}

/*-----------------------------------------------------------------------------+
 *  enet_rcv() handles the ethernet receive data
 *-----------------------------------------------------------------------------*/
static void enet_rcv (struct eth_device *dev, unsigned long malisr)
{
	unsigned long data_len;
	unsigned long rx_eob_isr;
	EMAC_4XX_HW_PST hw_p = dev->priv;

	int handled = 0;
	int i;
	int loop_count = 0;

	rx_eob_isr = mfdcr (MAL0_RXEOBISR);
	if ((0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL)) & rx_eob_isr) {
		/* clear EOB */
		mtdcr (MAL0_RXEOBISR, rx_eob_isr);

		/* EMAC RX done */
		while (1) {	/* do all */
			i = hw_p->rx_slot;

			if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
			    || (loop_count >= NUM_RX_BUFF))
				break;

			loop_count++;
			handled++;
			data_len = (unsigned long) hw_p->rx[i].data_len & 0x0fff;	/* Get len */
			if (data_len) {
				if (data_len > ENET_MAX_MTU)	/* Check len */
					data_len = 0;
				else {
					if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) {	/* Check Errors */
						data_len = 0;
						hw_p->stats.rx_err_log[hw_p->
								       rx_err_index]
							= hw_p->rx[i].ctrl;
						hw_p->rx_err_index++;
						if (hw_p->rx_err_index ==
						    MAX_ERR_LOG)
							hw_p->rx_err_index =
								0;
					}	/* emac_erros */
				}	/* data_len < max mtu */
			}	/* if data_len */
			if (!data_len) {	/* no data */
				hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY;	/* Free Recv Buffer */

				hw_p->stats.data_len_err++;	/* Error at Rx */
			}

			/* !data_len */
			/* AS.HARNOIS */
			/* Check if user has already eaten buffer */
			/* if not => ERROR */
			else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
				if (hw_p->is_receiving)
					printf ("ERROR : Receive buffers are full!\n");
				break;
			} else {
				hw_p->stats.rx_frames++;
				hw_p->stats.rx += data_len;
#ifdef INFO_4XX_ENET
				hw_p->stats.pkts_rx++;
#endif
				/* AS.HARNOIS
				 * use ring buffer
				 */
				hw_p->rx_ready[hw_p->rx_i_index] = i;
				hw_p->rx_i_index++;
				if (NUM_RX_BUFF == hw_p->rx_i_index)
					hw_p->rx_i_index = 0;

				hw_p->rx_slot++;
				if (NUM_RX_BUFF == hw_p->rx_slot)
					hw_p->rx_slot = 0;

				/*  AS.HARNOIS
				 * free receive buffer only when
				 * buffer has been handled (eth_rx)
				 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
				 */
			}	/* if data_len */
		}		/* while */
	}			/* if EMACK_RXCHL */
}


static int ppc_4xx_eth_rx (struct eth_device *dev)
{
	int length;
	int user_index;
	unsigned long msr;
	EMAC_4XX_HW_PST hw_p = dev->priv;

	hw_p->is_receiving = 1; /* tell driver */

	for (;;) {
		/* AS.HARNOIS
		 * use ring buffer and
		 * get index from rx buffer desciptor queue
		 */
		user_index = hw_p->rx_ready[hw_p->rx_u_index];
		if (user_index == -1) {
			length = -1;
			break;	/* nothing received - leave for() loop */
		}

		msr = mfmsr ();
		mtmsr (msr & ~(MSR_EE));

		length = hw_p->rx[user_index].data_len & 0x0fff;

		/* Pass the packet up to the protocol layers. */
		/*	 NetReceive(NetRxPackets[rxIdx], length - 4); */
		/*	 NetReceive(NetRxPackets[i], length); */
		invalidate_dcache_range((u32)hw_p->rx[user_index].data_ptr,
					(u32)hw_p->rx[user_index].data_ptr +
					length - 4);
		NetReceive (NetRxPackets[user_index], length - 4);
		/* Free Recv Buffer */
		hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
		/* Free rx buffer descriptor queue */
		hw_p->rx_ready[hw_p->rx_u_index] = -1;
		hw_p->rx_u_index++;
		if (NUM_RX_BUFF == hw_p->rx_u_index)
			hw_p->rx_u_index = 0;

#ifdef INFO_4XX_ENET
		hw_p->stats.pkts_handled++;
#endif

		mtmsr (msr);	/* Enable IRQ's */
	}

	hw_p->is_receiving = 0; /* tell driver */

	return length;
}

int ppc_4xx_eth_initialize (bd_t * bis)
{
	static int virgin = 0;
	struct eth_device *dev;
	int eth_num = 0;
	EMAC_4XX_HW_PST hw = NULL;
	u8 ethaddr[4 + CONFIG_EMAC_NR_START][6];
	u32 hw_addr[4];
	u32 mal_ier;

#if defined(CONFIG_440GX)
	unsigned long pfc1;

	mfsdr (SDR0_PFC1, pfc1);
	pfc1 &= ~(0x01e00000);
	pfc1 |= 0x01200000;
	mtsdr (SDR0_PFC1, pfc1);
#endif

	/* first clear all mac-addresses */
	for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++)
		memcpy(ethaddr[eth_num], "\0\0\0\0\0\0", 6);

	for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
		int ethaddr_idx = eth_num + CONFIG_EMAC_NR_START;
		switch (eth_num) {
		default:		/* fall through */
		case 0:
			eth_getenv_enetaddr("ethaddr", ethaddr[ethaddr_idx]);
			hw_addr[eth_num] = 0x0;
			break;
#ifdef CONFIG_HAS_ETH1
		case 1:
			eth_getenv_enetaddr("eth1addr", ethaddr[ethaddr_idx]);
			hw_addr[eth_num] = 0x100;
			break;
#endif
#ifdef CONFIG_HAS_ETH2
		case 2:
			eth_getenv_enetaddr("eth2addr", ethaddr[ethaddr_idx]);
#if defined(CONFIG_460GT)
			hw_addr[eth_num] = 0x300;
#else
			hw_addr[eth_num] = 0x400;
#endif
			break;
#endif
#ifdef CONFIG_HAS_ETH3
		case 3:
			eth_getenv_enetaddr("eth3addr", ethaddr[ethaddr_idx]);
#if defined(CONFIG_460GT)
			hw_addr[eth_num] = 0x400;
#else
			hw_addr[eth_num] = 0x600;
#endif
			break;
#endif
		}
	}

	/* set phy num and mode */
	bis->bi_phynum[0] = CONFIG_PHY_ADDR;
	bis->bi_phymode[0] = 0;

#if defined(CONFIG_PHY1_ADDR)
	bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
	bis->bi_phymode[1] = 0;
#endif
#if defined(CONFIG_440GX)
	bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
	bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
	bis->bi_phymode[2] = 2;
	bis->bi_phymode[3] = 2;
#endif

#if defined(CONFIG_440GX) || \
    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
    defined(CONFIG_405EX)
	ppc_4xx_eth_setup_bridge(0, bis);
#endif

	for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
		/*
		 * See if we can actually bring up the interface,
		 * otherwise, skip it
		 */
		if (memcmp (ethaddr[eth_num], "\0\0\0\0\0\0", 6) == 0) {
			bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
			continue;
		}

		/* Allocate device structure */
		dev = (struct eth_device *) malloc (sizeof (*dev));