lcdif: fix bridge shutdown

In dual mode (with lcdif and hdmi both used) Linux would end up
with built-in display flashing randomly at the top and otherwise
black screen. Instead of disabling the clocks, shut down the bridge
(SN65DSI86) exactly by spec and leave the clocks be.

Also increase the delay on init to make sure the bridge is up as
sometimes it did not respond in time, causing the display not work
in U-Boot.

board/boundary/nitrogen8m_som/lcdif.c

@@ -881,7 +881,7 @@ video_hw_init(void)
 	/* gpio3_io20 high: bridge on */
 	gpio_request(IMX_GPIO_NR(3, 20), "sn65dsi86_enable");
 	gpio_direction_output(IMX_GPIO_NR(3, 20), 1);
-	mdelay(200);
+	mdelay(400);
 
 	if(uclass_get_device_by_seq(UCLASS_I2C, 3, &i2cbus)){
 		err = "no i2c bus";
@@ -988,6 +988,16 @@ out:
 void
 video_hw_exit(void)
 {
+	/* backlight off */
+	gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
+	/* pwm2 off */
+	mr(pwm2, PWMCR, 0, CR_EN);
+	clock_enable(CCGR_PWM2, 0);
+	clock_set_target_val(PWM2_CLK_ROOT, 0);
+
+	/* bridge output off */
+	i2cwritebyte(bridge, 0x5a, 0x05);
+
 	/* gracefully shut down lcdif */
 	wr(lcdif, LCDIF_CTRL_CLR, CTRL_DOTCLK_MODE);
 	while(rr(lcdif, LCDIF_CTRL) & CTRL_RUN)
@@ -1009,22 +1019,12 @@ video_hw_exit(void)
 		;
 	wr(gpc, GPC_PGC_CPU_0_1_MAPPING, 0);
 
-	/* disable display clocks */
-	clock_enable(CCGR_DISPLAY, 0);
-	clock_enable(CCGR_SIM_DISPLAY, 0);
-
-	clock_set_target_val(MIPI_DSI_CORE_CLK_ROOT, 0);
-	clock_set_target_val(MIPI_DSI_PHY_REF_CLK_ROOT, 0);
-	clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, 0);
-	clock_set_target_val(DISPLAY_RTRM_CLK_ROOT, 0);
-	clock_set_target_val(DISPLAY_AXI_CLK_ROOT, 0);
-
-	/* turn off bridge */
+	/* ML_TX_MODE off */
+	i2cwritebyte(bridge, 0x96, 0);
+	/* DP lanes not configured */
+	i2cwritebyte(bridge, 0x93, 0);
+	/* DP PLL off */
+	i2cwritebyte(bridge, 0x0d, 0);
+	/* turn off the bridge */
 	gpio_direction_output(IMX_GPIO_NR(3, 20), 0);
-
-	/* turn off backlight pwm */
-	gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
-	wr(pwm2, PWMCR, CR_SWR);
-	clock_enable(CCGR_PWM2, 0);
-	clock_set_target_val(PWM2_CLK_ROOT, 0);
 }