Remove mnt4002 patch, superseded by ba9893e9

reform2-imx8mq/template-kernel/patches/mnt4002-imx-gpcv2-wake-smccc.patch

-diff --git a/drivers/irqchip/irq-imx-gpcv2.c b/drivers/irqchip/irq-imx-gpcv2.c
-index 7031ef44de4f..9cba81b5050d 100644
---- a/drivers/irqchip/irq-imx-gpcv2.c
-+++ b/drivers/irqchip/irq-imx-gpcv2.c
-@@ -17,6 +18,13 @@
- #define GPC_IMR1_CORE2		0x1c0
- #define GPC_IMR1_CORE3		0x1d0
- 
-+#define FSL_SIP_GPC                     0xC2000000
-+#define FSL_SIP_CONFIG_GPC_MASK         0x00
-+#define FSL_SIP_CONFIG_GPC_UNMASK       0x01
-+#define FSL_SIP_CONFIG_GPC_SET_WAKE     0x02
-+#define FSL_SIP_CONFIG_GPC_PM_DOMAIN    0x03
-+#define FSL_SIP_CONFIG_GPC_SET_AFF      0x04
-+#define FSL_SIP_CONFIG_GPC_CORE_WAKE    0x05
- 
- struct gpcv2_irqchip_data {
- 	struct raw_spinlock	rlock;
-@@ -76,12 +84,17 @@ static int imx_gpcv2_irq_set_wake(struct irq_data *d, unsigned int on)
- 	unsigned int idx = d->hwirq / 32;
- 	unsigned long flags;
- 	u32 mask, val;
-+	struct arm_smccc_res res;
- 
- 	raw_spin_lock_irqsave(&cd->rlock, flags);
- 	mask = BIT(d->hwirq % 32);
- 	val = cd->wakeup_sources[idx];
- 
- 	cd->wakeup_sources[idx] = on ? (val & ~mask) : (val | mask);
-+
-+	// save wakeup config in vendor tf-a
-+	arm_smccc_smc(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_SET_WAKE, d->hwirq, on, 0, 0, 0, 0, &res);
-+
- 	raw_spin_unlock_irqrestore(&cd->rlock, flags);
- 
- 	/*
-@@ -97,6 +110,7 @@ static void imx_gpcv2_irq_unmask(struct irq_data *d)
- 	struct gpcv2_irqchip_data *cd = d->chip_data;
- 	void __iomem *reg;
- 	u32 val;
-+	struct arm_smccc_res res;
- 
- 	raw_spin_lock(&cd->rlock);
- 	reg = gpcv2_idx_to_reg(cd, d->hwirq / 32);
-@@ -105,6 +119,10 @@ static void imx_gpcv2_irq_unmask(struct irq_data *d)
- 	writel_relaxed(val, reg);
- 	raw_spin_unlock(&cd->rlock);
- 
-+	// call into vendor tf-a
-+	//arm_smccc_smc(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_UNMASK,
-+	//							d->hwirq, 0, 0, 0, 0, 0, &res);
-+
- 	irq_chip_unmask_parent(d);
- }
- 
-@@ -113,12 +131,18 @@ static void imx_gpcv2_irq_mask(struct irq_data *d)
- 	struct gpcv2_irqchip_data *cd = d->chip_data;
- 	void __iomem *reg;
- 	u32 val;
-+	struct arm_smccc_res res;
- 
- 	raw_spin_lock(&cd->rlock);
- 	reg = gpcv2_idx_to_reg(cd, d->hwirq / 32);
- 	val = readl_relaxed(reg);
- 	val |= BIT(d->hwirq % 32);
- 	writel_relaxed(val, reg);
-+
-+	// call into vendor tf-a
-+	//arm_smccc_smc(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_MASK,
-+	//							d->hwirq, 0, 0, 0, 0, 0, &res);
-+
- 	raw_spin_unlock(&cd->rlock);
- 
- 	irq_chip_mask_parent(d);