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rkx7-litex-boards
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7a48a61605cf0551e618a2104476b9e123233685
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Created with Raphaël 2.2.0
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Dec
crosslink_nx_vip: Split camera MCLK to its own resource
targets/Ultrascale(+): Generate Reset to idelay clock domain (to be sure to follow UG571 reset sequence).
icebreaker: Lower VideoTerminal resolution to use default 24MHz sys_clk.
nexys4ddr: Integrate simple VideoFrameBuffer.
platforms/targets: Harmonize VGA pins and use new Video Terminal on all targets with VGA support.
icebreaker/nexys4ddr: Use new LiteXSoC's add_video_terminal method to add the Video Terminal.
targets/nexys4ddr: Replace VGA terminal with new LiteX's VideoTerminal.
icebreaker: Add optional DVI Video Terminal with new LiteX's VideoOut core.
Merge pull request #182 from hansfbaier/master
README.md: fix typo
Merge pull request #179 from shenki/arty-numato-sdcard-pmod
Merge branch 'master' into arty-numato-sdcard-pmod
targets/arty: rebase/merge PR179, rename adaptor to adapter.
Merge pull request #180 from hansfbaier/master
Add board support for Terasic/Arrow DECA board
arrow_sockit: Add README table entry and test target
Merge pull request #177 from antmicro/arty-dynamic-ip
targets/arty: Allow selection of sdcard mod adaptor
platforms/arty: Add numato sd card pmod
target/arty: add eth_dynamic_ip switch
targets/sds1104xe: Enable both Ethernet/Etherbone with hybrid LiteEthMAC.
Merge pull request #178 from yetifrisstlama/vc707_clk
platforms/sds1104xe: Integrate changes from https://github.com/360nosc0pe/scope.
Merge branch 'master' into vc707_clk
vc707: fix default clock frequency
targets/sds1104xe/BaseSoC: Enable Etherbone by default also defaults to Crossover UART when kwargs is empty.
Merge pull request #172 from hansfbaier/master
platforms/sds1104xe: fix ddram IOStandard (SSTL15, thanks @tmbinc) and add INTERNAL_VREF on ddram banks.
platform/de10nano: fix programmer (thanks @Godtec, see https://github.com/enjoy-digital/litex/pull/811).
sockit: Add an option to plug in an UART via the GPIO daughter board
Merge pull request #174 from yetifrisstlama/vc707_clk
vc707.py: clk156 add missing constraint
platforms/de0nano: directly use JP1 connector for serial pins.
Merge pull request #170 from hansfbaier/master
Merge pull request #171 from antmicro/symbiflow_nexys_video_support
use parameter for dram channel 0 or 1 and LedChaser
nexys_video: enable symbiflow toolchain
Merge pull request #169 from kazkojima/colorlight_i5-load
arrow_sockit: add support for MiSTer XS SDRAM modules
targets/colorlight_i5: use .bit stream instead of .svf when loading.
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