- Jul 06, 2021
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Joey Bushagour authored
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- Apr 12, 2021
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Shinken Sanada authored
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- Mar 29, 2021
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Florent Kermarrec authored
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Florent Kermarrec authored
- main_ram mem_map is now directly used by add_sdram when origin is None. - max_sdram_size/min_l2_data_width are no longer exposed as targets arguments this can still be used enforced directly in the few cases it is useful.
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- Mar 25, 2021
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Florent Kermarrec authored
boards: Add Vendor prefix to platforms/targets name when useful and when multiple boards from the same vendor. (With Retro-Compat on the imports).
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Florent Kermarrec authored
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- Mar 24, 2021
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Florent Kermarrec authored
targets: Switch to soc_core_args/soc_core_argdict (instead of soc_sdram that is now deprecated, but still supported for now).
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- Jan 07, 2021
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Florent Kermarrec authored
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- Jan 06, 2021
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Florent Kermarrec authored
The SoC reset added recently creates a path between sys_clk and pll.clkin clock domains that is reported by the tools but that can be safely ignored.
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- Dec 29, 2020
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Florent Kermarrec authored
./arty.py --variant=a7-35 or a7-100 ./arty_s7.py --variant=s7-50 or s7-25
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- Nov 12, 2020
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Florent Kermarrec authored
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- Nov 04, 2020
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Florent Kermarrec authored
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- Oct 13, 2020
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Florent Kermarrec authored
targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it.
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- Aug 23, 2020
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Florent Kermarrec authored
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- Aug 06, 2020
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Florent Kermarrec authored
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- Jun 30, 2020
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Florent Kermarrec authored
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- May 21, 2020
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Florent Kermarrec authored
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- May 08, 2020
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Florent Kermarrec authored
Default to Chaser mode and similar user interface than GPIOOut.
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- May 05, 2020
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Florent Kermarrec authored
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- Apr 13, 2020
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Florent Kermarrec authored
arty_s7: fix copyrights, rename to arty_s7, various minor changes to make it similar to others targets.
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- Apr 12, 2020
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Staf Verhaegen authored
As the pin-out is totally different from the A7 board I did put this in a separate class and not as a variant of the Arty board. Used migen Arty S7 board file and Digilent xdc file as reference.
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- Mar 21, 2020
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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- Mar 20, 2020
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Florent Kermarrec authored
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- Feb 27, 2020
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Florent Kermarrec authored
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- Feb 11, 2020
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Florent Kermarrec authored
targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC)
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- Feb 03, 2020
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Florent Kermarrec authored
We initially wanted to provide different level of support for the platforms/targets, mainly to avoid too much maintenance and let each contributor update its contributed platforms and targets, but it's easier to update all platforms/targets all-together when LiteX evolves or changes (and that's what has been done on litex-boards since the creation of the repository). So let just simplify things and avoid this differentiation.
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- Jan 16, 2020
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Florent Kermarrec authored
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- Jan 13, 2020
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Florent Kermarrec authored
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- Dec 06, 2019
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Florent Kermarrec authored
targets: keep attributes are no longer needed since automatically added when applying constraints to signals.
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- Dec 03, 2019
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Florent Kermarrec authored
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- Oct 30, 2019
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Florent Kermarrec authored
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- Oct 29, 2019
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Gabriel Somlo authored
Sync up with litex commit #201218b2c.
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- Oct 09, 2019
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Florent Kermarrec authored
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- Aug 26, 2019
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Florent Kermarrec authored
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- Jul 12, 2019
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Florent Kermarrec authored
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- Jun 24, 2019
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Florent Kermarrec authored
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- Jun 10, 2019
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Florent Kermarrec authored
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