- main_ram mem_map is now directly used by add_sdram when origin is None.
- max_sdram_size/min_l2_data_width are no longer exposed as targets arguments this can
still be used enforced directly in the few cases it is useful.

targets: Switch to soc_core_args/soc_core_argdict (instead of soc_sdram that is now deprecated, but still supported for now).

Collect --with-ethernet/--with-etherbone, --with-spi-sdcard/--with-sdcard,
etc. into ArgumentParser.add_mutually_exclusive_group()s.  That way, we
get pretty --help output, and appropriate error messages if somebody
tries to ask for something that doesn't make sense.

targets/ecp5: update clocking on boards with DDR3 to use reset from ddrphy.init and use primary clock for Power on reset.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>

Default to Chaser mode and similar user interface than GPIOOut.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>

targets: default to trellis toolchain on all ECP5 targets (now able to build all supported targets).

targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC)

We initially wanted to provide different level of support for the platforms/targets, mainly
to avoid too much maintenance and let each contributor update its contributed platforms and
targets, but it's easier to update all platforms/targets all-together when LiteX evolves or
changes (and that's what has been done on litex-boards since the creation of the repository).
So let just simplify things and avoid this differentiation.

Sync up with Litex commit #49372852d.