boards: Add Vendor prefix to platforms/targets name when useful and when multiple boards from the same vendor. (With Retro-Compat on the imports).

The SoC reset added recently creates a path between sys_clk and pll.clkin
clock domains that is reported by the tools but that can be safely ignored.

targets/pcie: remove force of csr_data_width to 32 (this is now the default) but just add a check on the pcie block.

Tested with:
./forest_kitten_33.py --uart-name=jtag_uart --build --load
litex/tools/litex_jtag_uart.py
lxterm /dev/pts/X

Default to Chaser mode and similar user interface than GPIOOut.