- main_ram mem_map is now directly used by add_sdram when origin is None.
- max_sdram_size/min_l2_data_width are no longer exposed as targets arguments this can
still be used enforced directly in the few cases it is useful.

boards: Add Vendor prefix to platforms/targets name when useful and when multiple boards from the same vendor. (With Retro-Compat on the imports).

targets: Switch to soc_core_args/soc_core_argdict (instead of soc_sdram that is now deprecated, but still supported for now).

The SoC reset added recently creates a path between sys_clk and pll.clkin
clock domains that is reported by the tools but that can be safely ignored.

targets/pcie: simplify using new LiteX's add_pcie method and enable it on all devices supported by LitePCIe.

targets/pcie: remove force of csr_data_width to 32 (this is now the default) but just add a check on the pcie block.

targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it.

DNA/XADC/ICAP are demonstrated in LitePCIe repository and should probably be added with
a add_xy method.

Default to Chaser mode and similar user interface than GPIOOut.

Should be compatible with software from: https://github.com/enjoy-digital/netv2.

We initially wanted to provide different level of support for the platforms/targets, mainly
to avoid too much maintenance and let each contributor update its contributed platforms and
targets, but it's easier to update all platforms/targets all-together when LiteX evolves or
changes (and that's what has been done on litex-boards since the creation of the repository).
So let just simplify things and avoid this differentiation.

aller/tagus/nereid: use crossover UART, rename SoC to PCIe SoC and pass soc_sdram_argdict to PCIeSoC