- main_ram mem_map is now directly used by add_sdram when origin is None.
- max_sdram_size/min_l2_data_width are no longer exposed as targets arguments this can
still be used enforced directly in the few cases it is useful.

boards: Add Vendor prefix to platforms/targets name when useful and when multiple boards from the same vendor. (With Retro-Compat on the imports).

targets: Switch to soc_core_args/soc_core_argdict (instead of soc_sdram that is now deprecated, but still supported for now).

targets/Ultrascale(+): Generate Reset to idelay clock domain (to be sure to follow UG571 reset sequence).

The SoC reset added recently creates a path between sys_clk and pll.clkin
clock domains that is reported by the tools but that can be safely ignored.

targets/pcie: simplify using new LiteX's add_pcie method and enable it on all devices supported by LitePCIe.

targets/pcie: remove force of csr_data_width to 32 (this is now the default) but just add a check on the pcie block.

targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it.

Tested with:
./forest_kitten_33.py --uart-name=jtag_uart --build --load
litex/tools/litex_jtag_uart.py
lxterm /dev/pts/X

Default to Chaser mode and similar user interface than GPIOOut.