- main_ram mem_map is now directly used by add_sdram when origin is None.
- max_sdram_size/min_l2_data_width are no longer exposed as targets arguments this can
still be used enforced directly in the few cases it is useful.

boards: Add Vendor prefix to platforms/targets name when useful and when multiple boards from the same vendor. (With Retro-Compat on the imports).

targets: Switch to soc_core_args/soc_core_argdict (instead of soc_sdram that is now deprecated, but still supported for now).

The SoC reset added recently creates a path between sys_clk and pll.clkin
clock domains that is reported by the tools but that can be safely ignored.

./arty.py --variant=a7-35 or a7-100
./arty_s7.py --variant=s7-50 or s7-25

targets/xilinx: use generic name for idelay clk (avoid clk200, clk400, etc...) since we somtimes want to change it.

Default to Chaser mode and similar user interface than GPIOOut.

arty_s7: fix copyrights, rename to arty_s7, various minor changes to make it similar to others targets.

As the pin-out is totally different from the A7 board I did put this
in a separate class and not as a variant of the Arty board.
Used migen Arty S7 board file and Digilent xdc file as reference.

targets/EthernetSoC: be sure memory region is added before adding Wishbone Slave (required by new SoC)

We initially wanted to provide different level of support for the platforms/targets, mainly
to avoid too much maintenance and let each contributor update its contributed platforms and
targets, but it's easier to update all platforms/targets all-together when LiteX evolves or
changes (and that's what has been done on litex-boards since the creation of the repository).
So let just simplify things and avoid this differentiation.

targets: keep attributes are no longer needed since automatically added when applying constraints to signals.

Sync up with litex commit #201218b2c.