targets: Switch to soc_core_args/soc_core_argdict (instead of soc_sdram that is now deprecated, but still supported for now).

nexys4ddr: add pmod connectors, and optional sdcard on pmodd

fix #848: allow ram initialization in bitstream to enable block ram 

fix #848: allow ram initialization in bitstream to enable block ram inference for ROM/RAM with initial value

arrow_sockit: get video terminal working on VGA

targets/nexys_video: Revert clk100 to avoid breaking Linux-on-LiteX-VexRiscv (we'll remove it when the switch the simple framebuffer will be done).

alveo_u280: Fix copyrights (avoid too much cascading on Platforms/Targets) and generate reset on idelay clock domain (similarly to recent change on others Ultrascale+ boards).

Alveo U280 board

crosslink_nx_vip: Remove constraints for hard MIPI pins

arty: Add an option to enable jtagbone

targets/versa_ecp5: Fix LiteEthPHYRMGII tx/rx delays (need to be updated due to a bug fix in the ECP5RGMII PHY).

Signed-off-by: gatecat <gatecat@ds0.me>

Then adds jtagbone for arty.  I have tested with the following
litex_server and it seems to work fine.

  litex_server --jtag --jtag-config openocd_xc7_ft2232.cfg

Note, the jtagbone and etherbone may be mutually exclusive, but I am not
sure how to define that in the args.

crosslink_nx_vip: Camera IO fixes

Signed-off-by: gatecat <gatecat@ds0.me>

Signed-off-by: gatecat <gatecat@ds0.me>

targets/Ultrascale(+): Generate Reset to idelay clock domain (to be sure to follow UG571 reset sequence).

Tested with: ./icebreaker.py --cpu-type=serv --with-video-terminal --build --flash

https://twitter.com/enjoy_digital/status/1365324823447171074

README.md: fix typo

Numato sdcard pmod for Arty

Add board support for Terasic/Arrow DECA board (Intel Max10)