The SoCCore definition used to be available under litex.soc.integration,
however it was removed in
https://github.com/enjoy-digital/litex/commit/626533ce9d84ba081aa320dd330f5f0d800333b0



Signed-off-by: Sean Cross <sean@xobs.io>

Fomu Hacker supports dual spi, so add a "spiflash4x" definition.
The litex spi_flash module will run this flash in dual mode, because the
`dq` array is only two signals wide.

Signed-off-by: Sean Cross <sean@xobs.io>

This documentation can be fetched using a package such as lxsocdoc.

Signed-off-by: Sean Cross <sean@xobs.io>

These pins were swapped in the definition, which made them not work so
well.

Signed-off-by: Sean Cross <sean@xobs.io>

platforms/target: only catch ModuleNotFoundError exceptions to improve error reporting (thanks mwelling)

Gls sync litex

Sync up with Litex commit #49372852d.

Sync up with litex commit #201218b2c.

Sync up with litex commit #ae9c25b74.

memory device selection for ulx3s

add sys clock freq flag, uses same method as current versa code

This connector is for the six "debug" pins on the Raspberry Pi header.

Signed-off-by: Sean Cross <sean@xobs.io>

The D3 and D4 pins were swapped around, leading to interesting issues.

Signed-off-by: Sean Cross <sean@xobs.io>

Fomu cpu updates

Signed-off-by: Sean Cross <sean@xobs.io>

The heap placer is important enough that we should just make it the
default.

Also, add a `USBSoC` that includes the required interrupt table, as this
must be specified prior to calling `__init__()`.

Signed-off-by: Sean Cross <sean@xobs.io>

Use the memory array to find the address for the sram bank.

Signed-off-by: Sean Cross <sean@xobs.io>

Allow the user to specify a CPU.

Signed-off-by: Sean Cross <sean@xobs.io>

partner: add platforms and targets for aller, tagus and nereid boards

partner: add fomu target

This adds the Fomu target back in.  The default BaseSoC supports
various USB methods, and will be updated as more become available.

The debug bridge may optionally be added.

Signed-off-by: Sean Cross <sean@xobs.io>