- Sep 01, 2021
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Florent Kermarrec authored
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Florent Kermarrec authored
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enjoy-digital authored
lattice_crosslink_nx_evn: don't set MASTER_SPI_PORT=SERIAL
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Florent Kermarrec authored
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Dan Callaghan authored
Setting MASTER_SPI_PORT=SERIAL causes the SPI flash pins to be reserved for use by the sysCONFIG logic, and prevents user logic from assigning them. This made it impossible to have a Litex design which accesses the SPI flash on this board. Remove the setting, so that we get the default behaviour which permits user logic to assign these pins. In the unlikely event that someone needs the pins to stay reserved for sysCONFIG after configuration (I'm not sure why this would be needed) they could explicitly add this command in their design.
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enjoy-digital authored
lattice_crosslink_nx_evn: allow specifying the FPGA device
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Florent Kermarrec authored
- Now uses regular UART. - Build tested with: ./quertyembedded_beaglewire.py --cpu-type=serv --build - Can still be build with Crossover UART with --uart-name=crossover+bridge.
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Florent Kermarrec authored
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enjoy-digital authored
beaglewire platform and target added
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Florent Kermarrec authored
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enjoy-digital authored
WIP: Initial PYNQ Z2 support
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- Aug 31, 2021
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enjoy-digital authored
FIX: OrangeCrab Feather SPI pad name
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Florent Kermarrec authored
ebaz4205: Remove PS7 support for now (since untested and we'll avoid the .xci in LiteX-Boards repository).
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Dhiru Kholia authored
Usage: ``` ./ebaz4205.py --cpu-type=vexriscv --build --load ``` ``` $ pwd litex-boards/litex_boards/targets ``` Tip: Use `GTKTerm` to connect to /dev/ttyUSB0 (usually) and interact with the LiteX BIOS. References: - https://github.com/fusesoc/blinky#ebaz4205-development-board - https://github.com/olofk/serv/#ebaz4205-development-board - https://github.com/xjtuecho/EBAZ4205#ebaz4205 - https://github.com/nmigen/nmigen-boards/pull/180 (merged) - https://github.com/olofk/corescore/pull/33 - The existing 'Zybo Z7' example Note: The `PS7` stuff remains untested via LiteX for now.
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- Aug 30, 2021
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Yoshimasa Niwa authored
**Problems** `SPIMaster` pad names are `clk`, `cs_n`, `mosi`, and `miso`. However, `feather_spi` is using `sck` instead of `clk`, therefore it is not able to use as-is for `SPIMaster`, for example, with `add_spi` on Linux On LiteX VexRiscv. **Solution** In fact, `spisdcard` and other SPI related pad names are using `clk`, only `feather_spi` is using `sck`. Therefore, rename `sck` to `clk`.
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- Aug 23, 2021
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Florent Kermarrec authored
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- Aug 17, 2021
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Dan Callaghan authored
This board is documented as having the LIFCL-40-9BG400C part, but some versions of the board exist which were fitted with LIFCL-40-8BG400CES, an engineering sample part. The distinction is important because the engineering sample requires a different device ID to be embedded in the bitstream. If you try to build a bitstream for LIFCL-40-9BG400C and load it onto LIFCL-40-8BG400CES the configuration fails (indicated by the red "INITN" LED on this board). Accept --device to allow the user to specify which FPGA part their board has.
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- Aug 16, 2021
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Tim Ansell authored
update IRC channel in README
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alainlou authored
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ombhilare999 authored
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- Aug 13, 2021
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Martin Troiber authored
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- Aug 11, 2021
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enjoy-digital authored
colorlight_5a_75x: Disable full_memory_we for l2 cache by default
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- Aug 08, 2021
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David Sawatzke authored
Leads to an increase in DP16KD, first noticed in https://github.com/enjoy-digital/liteeth/issues/70. With full_mem_we: ``` Info: DP16KD: 41/ 56 73% ``` Without: ``` Info: DP16KD: 29/ 56 51% ```
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- Jul 30, 2021
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Florent Kermarrec authored
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Florent Kermarrec authored
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- Jul 29, 2021
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
targets: Remove old call to add_spi_flash on targets now using LiteSPI (we'll find it with gitk is required).
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- Jul 28, 2021
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Florent Kermarrec authored
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enjoy-digital authored
Add option for different Fomu SPI ICs.
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Sergiu Mosanu authored
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Joey Bushagour authored
Signed-off-by:
Joey Bushagour <jbushagour@google.com>
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Florent Kermarrec authored
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Florent Kermarrec authored
This is now required since ECP5PLL now checks that PFD is in required range.
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Florent Kermarrec authored
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Florent Kermarrec authored
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Florent Kermarrec authored
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