zybo_z7: fix clock pin constraint

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>

targets/orangecrab: Fix --sdram-device help text

Obviously --sdram-device takes the SDRAM device, not the ECP5 FPGA
device.

Fixes: bf3c9dc9 ("orangecrab: Add sdram selection option")
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>

Following commits make it generic/portable while still using IOBuffers:
https://github.com/litex-hub/valentyusb/commit/77b9d010586755a0e0c3b47d20aa387472d0ef7f
https://github.com/litex-hub/valentyusb/commit/371526e432a858b768ddc561cee0d7a0c8f40f42

add support for redpitaya14/16

nexus: Allow selection of toolchain

Signed-off-by: David Shah <dave@ds0.me>

targets/colorlight_5a_75x: update instructions and LiteEthPHYRGMII's tx_delay (required with LiteEth fixes).

mercury_xu5: reduce cmd_latency to fix problems with DRAM leveling

Support for the RHS Research LiteFury

LiteFury is an Artix-7 development board in the M.2 form factor
for PCIe accelerator development. It's similar to the Aller but
with an xc7a100t rather than an xc7a200t and no TPM module.

https://rhsresearch.com/collections/rhs-public/products/litefury

Pinout from https://github.com/360nosc0pe project.

targets/pcie: simplify using new LiteX's add_pcie method and enable it on all devices supported by LitePCIe.

add Qmtech EP4CE15 coreboard support

ex of use:
./simple.py litex_boards.platform.ulx3s --build --load
./simple.py litex_boards.platform.trellisboard --build --load
./simple.py litex_boards.platform.arty --build --load
etc...

Required to simplify simple.py target and use trellis/icestorm as default toolchain.

targets/pcie: remove force of csr_data_width to 32 (this is now the default) but just add a check on the pcie block.