targets/ac701: reduce ddram pads to the first 4 modules.

litex_boards/targets/ac701.py

@@ -20,6 +20,7 @@ from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
 from litex.soc.cores.led import LedChaser
 
+from litedram.common import PHYPadsReducer
 from litedram.modules import MT8JTF12864
 from litedram.phy import s7ddrphy
 
@@ -65,7 +66,8 @@ class BaseSoC(SoCCore):
 
         # DDR3 SDRAM -------------------------------------------------------------------------------
         if not self.integrated_main_ram_size:
-            self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
+            self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
+                pads         = PHYPadsReducer(platform.request("ddram"), [0, 1, 2, 3]),
                 memtype      = "DDR3",
                 nphases      = 4,
                 sys_clk_freq = sys_clk_freq)