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Commit 7fa22a49 authored by Florent Kermarrec's avatar Florent Kermarrec
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arty: Switch SPI Flash rate to 1:2 (DDR) (Possible on Arty since SPI Flash's...

arty: Switch SPI Flash rate to 1:2 (DDR) (Possible on Arty since SPI Flash's clk does not require use of STARTUPE2).

On the Digilent Arty, the SPI Flash's clk is connected to CCLK (that can be driven
through the STARTUPE2) but also to another generic IO that can be use to drive the
clock through DDR primitives.
parent aa220972
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...@@ -103,7 +103,7 @@ class BaseSoC(SoCCore): ...@@ -103,7 +103,7 @@ class BaseSoC(SoCCore):
if with_spi_flash: if with_spi_flash:
from litespi.modules import S25FL128L from litespi.modules import S25FL128L
from litespi.opcodes import SpiNorFlashOpCodes as Codes from litespi.opcodes import SpiNorFlashOpCodes as Codes
self.add_spi_flash(mode="4x", module=S25FL128L(Codes.READ_1_1_4), with_master=True) self.add_spi_flash(mode="4x", module=S25FL128L(Codes.READ_1_1_4), rate="1:2", with_master=True)
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------
if with_led_chaser: if with_led_chaser:
......
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