targets/Ultrascale(+): enable USDDRPHY_DEBUG.

litex_boards/targets/kcu105.py

@@ -68,6 +68,7 @@ class BaseSoC(SoCCore):
                 cmd_latency      = 0)
             self.add_csr("ddrphy")
             self.add_constant("USDDRPHY", None)
+            self.add_constant("USDDRPHY_DEBUG", None)
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,
                 module                  = EDY4016A(sys_clk_freq, "1:4"),

litex_boards/targets/mercury_xu5.py

@@ -67,6 +67,7 @@ class BaseSoC(SoCCore):
                 cmd_latency      = 0)
             self.add_csr("ddrphy")
             self.add_constant("USDDRPHY", None)
+            self.add_constant("USDDRPHY_DEBUG", None)
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,
                 module                  = MT40A256M16(sys_clk_freq, "1:4"),

litex_boards/targets/vcu118.py

@@ -67,6 +67,7 @@ class BaseSoC(SoCCore):
                 cmd_latency      = 0)
             self.add_csr("ddrphy")
             self.add_constant("USDDRPHY", None)
+            self.add_constant("USDDRPHY_DEBUG", None)
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,
                 module                  = EDY4016A(sys_clk_freq, "1:4"),

litex_boards/targets/zcu104.py

@@ -66,6 +66,7 @@ class BaseSoC(SoCCore):
                 cmd_latency      = 1)
             self.add_csr("ddrphy")
             self.add_constant("USDDRPHY", None)
+            self.add_constant("USDDRPHY_DEBUG", None)
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,
                 module                  = KVR21SE15S84(sys_clk_freq, "1:4"),