also patch ini file for new ddr blob path

0001-ini-ddrbin-bump.patch

+diff --git a/rock5b-rk3588.ini b/rock5b-rk3588.ini
+index bdf1f38a..084a5ca6 100755
+--- a/rock5b-rk3588.ini
++++ b/rock5b-rk3588.ini
+@@ -5,7 +5,7 @@ MAJOR=1
+ MINOR=11
+ [CODE471_OPTION]
+ NUM=1
+-Path1=../rkbin/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2736MHz_v1.08.bin
++Path1=../rkbin/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.16.bin
+ Sleep=1
+ [CODE472_OPTION]
+ NUM=1
+@@ -14,7 +14,7 @@ Path1=spl/u-boot-spl.bin
+ NUM=2
+ LOADER1=FlashData
+ LOADER2=FlashBoot
+-FlashData=../rkbin/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2736MHz_v1.08.bin
++FlashData=../rkbin/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.16.bin
+ FlashBoot=spl/u-boot-spl.bin
+ [OUTPUT]
+ PATH=rock5b-rk3588.bin

build.sh

@@ -19,6 +19,7 @@ cp *.dts u-boot/arch/arm/dts/
 cp *_defconfig u-boot/configs/
 cd u-boot
 patch -p1 <../0000-dts-makefile.patch
+patch -p1 <../0001-ini-ddrbin-bump.patch
 patch -p1 <../PATCH-v2-clk-rockchip-rk3588-Set-SPLL-frequency-during-SPL-stage.patch
 export ROCKCHIP_TPL=../rkbin/bin/rk35/rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.16.bin
 export BL31=../trusted-firmware-a/build/rk3588/release/bl31/bl31.elf