.gitlab-ci.yml

@@ -20,7 +20,7 @@ stages:
   before_script: |
     set -x
     apt-get update -o Acquire::AllowReleaseInfoChange=true -o quiet::ReleaseInfoChange=true
-    apt-get --no-install-recommends -y install devscripts reprepro sbuild debhelper debian-keyring quilt pristine-tar rsync git python3-debian faketime python3-jinja2 uidmap debian-archive-keyring curl
+    apt-get --no-install-recommends -y install devscripts reprepro sbuild debhelper debian-keyring quilt pristine-tar rsync git python3-debian faketime python3-jinja2 python3-dacite uidmap debian-archive-keyring curl
     if [ ! -e /proc/sys/fs/binfmt_misc/status ]; then
       mount -t binfmt_misc binfmt_misc /proc/sys/fs/binfmt_misc
     fi
@@ -31,10 +31,11 @@ stages:
     runuser -u build -- sh -c 'mkdir -p changes buildlogs ~/.cache/sbuild'
     if [ "$BASESUITE" = "experimental" ]; then
       runuser -u build -- sh -c 'ln -s unstable-amd64.tar ~/.cache/sbuild/experimental-amd64.tar'
-      BASESUITE=unstable
     fi
-    runuser -u build -- sh -c "cp chroot-amd64.tar ~/.cache/sbuild/$BASESUITE-amd64.tar"
-    runuser -u build -- sh -c "cp chroot-arm64.tar ~/.cache/sbuild/$BASESUITE-arm64.tar"
+    for arch in amd64 arm64; do
+      # running in a runuser sub-shell to properly expand ~
+      runuser -u build -- sh -c "cp chroot-${arch}.tar ~/.cache/sbuild/$([ "$BASESUITE" = "experimental" ] && echo unstable || echo "$BASESUITE")-$arch.tar"
+    done
     chown build -R .
 
 setup:
@@ -47,6 +48,22 @@ setup:
       - chdist
   script: |
     set -x
+    # do not allow custom builds on the main branch as those would taint the
+    # repository at https://mntre.com/reform-debian-repo/
+    if [ "$CI_SERVER_HOST" = "source.mnt.re" ] && [ "x$CI_COMMIT_BRANCH" = xmain -o "x$CI_COMMIT_REF_NAME" = xmain ]; then
+      if [ "$BASESUITE" != "unstable" ]; then
+        echo "refusing to run pipeline on the main branch with BASESUITE not set to 'unstable'" >&2
+        exit 1
+      fi
+      if [ "$OURSUITE" != "reform" ]; then
+        echo "refusing to run pipeline on the main branch with OURSUITE not set to 'reform'" >&2
+        exit 1
+      fi
+      if [ "$REFORM_TOOLS_BRANCH" != "main" ]; then
+        echo "refusing to run pipeline on the main branch with REFORM_TOOLS_BRANCH not set to 'main'" >&2
+        exit 1
+      fi
+    fi
     apt-get update -o Acquire::AllowReleaseInfoChange=true -o quiet::ReleaseInfoChange=true
     apt-get --no-install-recommends -y install reprepro python3 devscripts mmdebstrap uidmap
     if [ ! -e /proc/sys/fs/binfmt_misc/status ]; then
@@ -57,15 +74,12 @@ setup:
     adduser --comment build --disabled-password build
     chown build -R .
     rm -rvf changes buildlogs chdist repo chroot-amd64.tar chroot-arm64.tar
-    if [ "$BASESUITE" = "experimental" ]; then
-      BASESUITE=unstable
-    fi
     runuser -u build -- mmdebstrap --architecture=amd64 --variant=buildd --mode=unshare \
       --chrooted-customize-hook='rm /usr/bin/ischroot && ln -s /bin/true /usr/bin/ischroot' ${IFS# DebianBug:1056385} \
-      $BASESUITE chroot-amd64.tar
+      "$([ "$BASESUITE" = "experimental" ] && echo unstable || echo "$BASESUITE")" chroot-amd64.tar
     runuser -u build -- mmdebstrap --architecture=arm64 --variant=buildd --mode=unshare \
       --chrooted-customize-hook='rm /usr/bin/ischroot && ln -s /bin/true /usr/bin/ischroot' ${IFS# DebianBug:1056385} \
-      $BASESUITE chroot-arm64.tar
+      "$([ "$BASESUITE" = "experimental" ] && echo unstable || echo "$BASESUITE")" chroot-arm64.tar
     runuser -u build -- sh -x ./setup.sh
 
 build_patched:
@@ -103,6 +117,9 @@ build_patched:
         done
       fi
     done
+    if [ "$BASESUITE" = "experimental" ]; then
+      BASESUITE=unstable
+    fi
     runuser -u build -- sh -x ./build_patched.sh 2>&1 | ./filter-output
 
 build_custom:
@@ -136,8 +153,11 @@ build_linux:
       - changes
       - linux/linux_*_arm64-*.build
   script: |
-    runuser -u build -- sh -xc '. ./common.sh; cd linux; . ./build.sh' 2>&1 | ./filter-output
+    runuser -u build -- sh -xc '. ./common.sh; cd linux; export BASESUITE=unstable; . ./build.sh' 2>&1 | ./filter-output
     dpkg-deb -c changes/linux-image-*-reform2-arm64_*_arm64.deb | grep 'kernel/drivers/gpu/drm/imx\(/cdns\)\?/cdns_mhdp_imx.ko'
+    echo "BASESUITE: $BASESUITE"
+    echo "OURSUITE: $OURSUITE"
+    echo "REFORM_TOOLS_BRANCH: $REFORM_TOOLS_BRANCH"
 
 reprepro:
   stage: reprepro
@@ -150,12 +170,15 @@ reprepro:
     when: always
     paths:
       - repo
+      - variables.sh
   script: |
     set -x
     apt-get update -o Acquire::AllowReleaseInfoChange=true -o quiet::ReleaseInfoChange=true
     apt-get --no-install-recommends -y install reprepro python3 devscripts
     adduser --comment build --disabled-password build
     runuser -u build -- sh -x ./reprepro.sh
-    echo "BASESUITE: $BASESUITE"
-    echo "OURSUITE: $OURSUITE"
-    echo "REFORM_TOOLS_BRANCH: $REFORM_TOOLS_BRANCH"
+    {
+      echo "BASESUITE=\"$BASESUITE\"";
+      echo "OURSUITE=\"$OURSUITE\"";
+      echo "REFORM_TOOLS_BRANCH=\"$REFORM_TOOLS_BRANCH\"";
+    } | tee variables.sh

README.md

@@ -66,3 +66,8 @@ Scripts for running the reform.
 To just rebuild the kernel and not the rest, you can run this:
 
     sh -xc '. ./setup.sh; cd linux; . ./build.sh'
+
+You can also build the kernel of a specific suite by setting `BASESUITE` to the
+suite name like `experimental` in this example:
+
+    sh -xc 'BASESUITE=experimental; . ./setup.sh; cd linux; . ./build.sh'

common.sh

@@ -48,7 +48,7 @@ SRC_LIST_PATCHED="deb [ trusted=yes ] http://127.0.0.1:$HTTP_PORT/ $OURSUITE mai
 BUILD_ARCH=$(dpkg --print-architecture)
 HOST_ARCH=arm64
 
-export DEB_BUILD_OPTIONS="noautodbgsym nocheck noudeb parallel=16"
+export DEB_BUILD_OPTIONS="noautodbgsym nocheck noudeb"
 
 chdistdata=$(pwd)/chdist
 chdist_base() {

linux/build.sh

@@ -47,33 +47,70 @@ faketime=
 if command -v faketime >/dev/null && [ -n "${SOURCE_DATE_EPOCH:+x}" ]; then
 	faketime="faketime @$SOURCE_DATE_EPOCH"
 fi
-env --chdir=linux TZ=UTC $faketime dch --local "+$VERSUFFIX$datesuffix" "apply mnt reform patch"
+
+DEB_VERSION="$(dpkg-parsechangelog --show-field Version --file linux/debian/changelog)"
+DEB_VERSION_UPSTREAM="$(echo "$DEB_VERSION" | sed -e 's/-[^-]*$//')"
+KVER=$(echo "$DEB_VERSION" | sed 's/\([0-9]\+\.[0-9]\+\).*/\1/')
+if dpkg --compare-versions "$KVER" ge "6.7"; then
+	oldversion="$(dpkg-parsechangelog --show-field=Version --file linux/debian/changelog)"
+	newversion="$(echo "$oldversion" | sed 's/\([0-9.]\+\)\(.*\)/\1-reform2\2/')"
+	env --chdir=linux TZ=UTC $faketime dch --newversion "$newversion+$VERSUFFIX$datesuffix" "apply mnt reform patch"
+	mv "linux_$DEB_VERSION_UPSTREAM.orig.tar.xz" "linux_$DEB_VERSION_UPSTREAM-reform2.orig.tar.xz"
+else
+	env --chdir=linux TZ=UTC $faketime dch --local "+$VERSUFFIX$datesuffix" "apply mnt reform patch"
+fi
 env --chdir=linux TZ=UTC $faketime dch --force-distribution --distribution="$OURSUITE" --release ""
 
 env --chdir=linux patch -p1 < packaging.diff
 
-mkdir -p linux/debian/config.local/arm64/none
-cat << END >> linux/debian/config.local/defines
+# new toml config format since 6.7
+if dpkg --compare-versions "$KVER" ge "6.7"; then
+	mkdir -p linux/debian/config.local/arm64
+	cat << END >> linux/debian/config.local/arm64/defines.toml
+[[flavour]]
+name = 'arm64'
+[flavour.defs]
+is_default = true
+[flavour.packages]
+installer = false
+docs = false
+
+[[featureset]]
+name = 'none'
+
+[[featureset.flavour]]
+name = 'arm64'
+
+[build]
+enable_signed = false
+END
+else
+	mkdir -p linux/debian/config.local/arm64/none
+	cat << END >> linux/debian/config.local/defines
 [packages]
 installer: false
 docs: false
 END
-cat << END >> linux/debian/config.local/arm64/defines
+	cat << END >> linux/debian/config.local/arm64/defines
 [base]
 featuresets: none
 
 [build]
 signed-code: false
 END
-cat << END >> linux/debian/config.local/arm64/none/defines
+	cat << END >> linux/debian/config.local/arm64/none/defines
 [base]
 flavours: arm64
 END
+fi
 
 KVER=$(dpkg-parsechangelog --show-field Version --file linux/debian/changelog | sed 's/\([0-9]\+\.[0-9]\+\).*/\1/')
 
 # the abiname field was dropped in 6.6 with commit 3282bf29846a0c47a8e01c60c038d29ad17c573d
-if dpkg --compare-versions "$KVER" ge "6.6"; then
+# since 6.7 there is the new toml config format
+if dpkg --compare-versions "$KVER" ge "6.7"; then
+	: # nothing to do
+elif test "$KVER" = 6.6; then
 	# apply https://salsa.debian.org/kernel-team/linux/-/merge_requests/957
 	cat << END | env --chdir=linux patch -p1
 --- a/debian/bin/gencontrol.py
@@ -166,4 +203,4 @@ env --chdir=linux DEB_BUILD_PROFILES="$DEB_BUILD_PROFILES" \
 		--verbose --no-source-only-changes --no-run-lintian --no-run-autopkgtest
 
 mv "./linux_$(dpkg-parsechangelog --show-field Version --file linux/debian/changelog)_arm64.changes" "./linux.changes"
-dcmd cp "./linux.changes" "$ROOTDIR/changes"
+dcmd mv "./linux.changes" "$ROOTDIR/changes"

linux/patches6.7/imx8mp-mnt-pocket-reform/2ghz/0001-imx8mp-2ghz-clk.patch

+From 02e8c29cac92595796138bf756006635e404b507 Mon Sep 17 00:00:00 2001
+From: "Lukas F. Hartmann" <lukas@mntre.com>
+Date: Sun, 9 Jul 2023 22:19:22 +0200
+Subject: [PATCH 1/2] imx8mp-2ghz-clk
+
+---
+ drivers/clk/imx/clk-pll14xx.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+--- a/drivers/clk/imx/clk-pll14xx.c
++++ b/drivers/clk/imx/clk-pll14xx.c
+@@ -45,6 +45,8 @@ struct clk_pll14xx {
+ #define to_clk_pll14xx(_hw) container_of(_hw, struct clk_pll14xx, hw)
+ 
+ static const struct imx_pll14xx_rate_table imx_pll1416x_tbl[] = {
++	PLL_1416X_RATE(2400000000U, 300, 3, 0),
++	PLL_1416X_RATE(2000000000U, 250, 3, 0),
+ 	PLL_1416X_RATE(1800000000U, 225, 3, 0),
+ 	PLL_1416X_RATE(1600000000U, 200, 3, 0),
+ 	PLL_1416X_RATE(1500000000U, 375, 3, 1),
+@@ -253,7 +255,7 @@ static unsigned long clk_pll14xx_recalc_
+ 
+ 	if (pll->type == PLL_1443X) {
+ 		pll_div_ctl1 = readl_relaxed(pll->base + DIV_CTL1);
+-		kdiv = (s16)FIELD_GET(KDIV_MASK, pll_div_ctl1);
++		kdiv = FIELD_GET(KDIV_MASK, pll_div_ctl1);
+ 	} else {
+ 		kdiv = 0;
+ 	}

linux/patches6.7/imx8mp-mnt-pocket-reform/2ghz/0002-imx8mp-2ghz-opp.patch

+From 33e011e724aa70cb19c8c1fd6aa69a1addebe6de Mon Sep 17 00:00:00 2001
+From: "Lukas F. Hartmann" <lukas@mntre.com>
+Date: Sun, 9 Jul 2023 22:19:23 +0200
+Subject: [PATCH 2/2] imx8mp-2ghz-opp
+
+---
+ arch/arm64/boot/dts/freescale/imx8mp.dtsi | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+index 3dc2102cbb3d..d55db50df4a3 100644
+--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
++++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+@@ -158,6 +158,14 @@ opp-1800000000 {
+ 			clock-latency-ns = <150000>;
+ 			opp-suspend;
+ 		};
++
++		opp-2000000000 {
++			opp-hz = /bits/ 64 <1800000000>;
++			opp-microvolt = <1000000>;
++			opp-supported-hw = <0x20>, <0x3>;
++			clock-latency-ns = <150000>;
++			opp-suspend;
++		};
+ 	};
+ 
+ 	osc_32k: clock-osc-32k {
+-- 
+2.40.0
+

linux/patches6.7/imx8mp-mnt-pocket-reform/hdmi/0001-arm64-dts-imx8mp-add-HDMI-display-pipeline.patch

+From d582ee5aaa6ba28ab44a0fadd061d3a288a273b7 Mon Sep 17 00:00:00 2001
+From: Lucas Stach <l.stach@pengutronix.de>
+Date: Thu, 31 Mar 2022 22:53:14 +0200
+Subject: [PATCH 01/11] arm64: dts: imx8mp: add HDMI display pipeline
+
+This adds the DT nodes for all the peripherals that make up the
+HDMI display pipeline.
+
+Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
+---
+ arch/arm64/boot/dts/freescale/imx8mp.dtsi | 83 +++++++++++++++++++++++
+ 1 file changed, 83 insertions(+)
+
+--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
++++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+@@ -1569,6 +1569,89 @@
+ 					opp-hz = /bits/ 64 <1000000000>;
+ 				};
+ 			};
++
++			hdmi_pvi: display-bridge@32fc4000 {
++				compatible = "fsl,imx8mp-hdmi-pvi";
++				reg = <0x32fc4000 0x40>;
++				power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>;
++				status = "disabled";
++
++				ports {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					port@0 {
++						reg = <0>;
++						pvi_from_lcdif3: endpoint {
++							remote-endpoint = <&lcdif3_to_pvi>;
++						};
++					};
++
++					port@1 {
++						reg = <1>;
++						pvi_to_hdmi_tx: endpoint {
++							remote-endpoint = <&hdmi_tx_from_pvi>;
++						};
++					};
++				};
++			};
++
++			lcdif3: display-controller@32fc6000 {
++				compatible = "fsl,imx8mp-lcdif";
++				reg = <0x32fc6000 0x238>;
++				interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
++				interrupt-parent = <&irqsteer_hdmi>;
++				clocks = <&hdmi_tx_phy>,
++					 <&clk IMX8MP_CLK_HDMI_APB>,
++					 <&clk IMX8MP_CLK_HDMI_ROOT>;
++				clock-names = "pix", "axi", "disp_axi";
++				power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_LCDIF>;
++				status = "disabled";
++
++				port {
++					lcdif3_to_pvi: endpoint {
++						remote-endpoint = <&pvi_from_lcdif3>;
++					};
++				};
++			};
++
++			hdmi_tx: hdmi@32fd8000 {
++				compatible = "fsl,imx8mp-hdmi";
++				reg = <0x32fd8000 0x7eff>;
++				interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
++				interrupt-parent = <&irqsteer_hdmi>;
++				clocks = <&clk IMX8MP_CLK_HDMI_APB>,
++					 <&clk IMX8MP_CLK_HDMI_REF_266M>,
++					 <&clk IMX8MP_CLK_HDMI_FDCC_TST>,
++					 <&clk IMX8MP_CLK_32K>,
++					 <&hdmi_tx_phy>;
++				clock-names = "iahb", "isfr", "fdcc", "cec", "pix";
++				assigned-clocks = <&clk IMX8MP_CLK_HDMI_REF_266M>;
++				assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>;
++				power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>;
++				reg-io-width = <1>;
++				status = "disabled";
++
++				port {
++					hdmi_tx_from_pvi: endpoint {
++						remote-endpoint = <&pvi_to_hdmi_tx>;
++					};
++				};
++			};
++
++			hdmi_tx_phy: phy@32fdff00 {
++				compatible = "fsl,imx8mp-hdmi-phy";
++				reg = <0x32fdff00 0x100>;
++				clocks = <&clk IMX8MP_CLK_HDMI_APB>,
++					 <&clk IMX8MP_CLK_HDMI_24M>;
++				clock-names = "apb", "ref";
++				assigned-clocks = <&clk IMX8MP_CLK_HDMI_24M>;
++				assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
++				power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>;
++				#clock-cells = <0>;
++				#phy-cells = <0>;
++				status = "disabled";
++			};
+ 		};
+ 
+ 		aips4: bus@32c00000 {

linux/patches6.7/imx8mp-mnt-pocket-reform/hdmi/0002-arm64-dts-imx8mp-evk-enable-HDMI.patch

+From c658e0a392bd9887ccd4f45179e08adfa9b695b0 Mon Sep 17 00:00:00 2001
+From: Lucas Stach <l.stach@pengutronix.de>
+Date: Mon, 4 Apr 2022 19:45:03 +0200
+Subject: [PATCH 02/11] arm64: dts: imx8mp-evk: enable HDMI
+
+Enable the DT nodes for HDMI TX and PHY and add the pinctrl for the few
+involved pins that are configurable.
+
+Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
+---
+ arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 27 ++++++++++++++++++++
+ 1 file changed, 27 insertions(+)
+
+--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
++++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+@@ -299,6 +299,20 @@
+ 	status = "disabled";/* can2 pin conflict with pdm */
+ };
+ 
++&hdmi_pvi {
++	status = "okay";
++};
++
++&hdmi_tx {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_hdmi>;
++	status = "okay";
++};
++
++&hdmi_tx_phy {
++	status = "okay";
++};
++
+ &i2c1 {
+ 	clock-frequency = <400000>;
+ 	pinctrl-names = "default";
+@@ -552,6 +566,10 @@
+ 	status = "okay";
+ };
+ 
++&lcdif3 {
++	status = "okay";
++};
++
+ &snvs_pwrkey {
+ 	status = "okay";
+ };
+@@ -718,6 +736,15 @@
+ 		>;
+ 	};
+ 
++	pinctrl_hdmi: hdmigrp {
++		fsl,pins = <
++			MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL	0x1c3
++			MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA	0x1c3
++			MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD		0x19
++			MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC		0x19
++		>;
++	};
++
+ 	pinctrl_i2c1: i2c1grp {
+ 		fsl,pins = <
+ 			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c2

linux/patches6.7/imx8mp-mnt-pocket-reform/hdmi/0004-dt-bindings-display-imx-add-binding-for-i.MX8MP-HDMI.patch

+From 7b1066c335ef49406b623dde6a70d39d8c58dde8 Mon Sep 17 00:00:00 2001
+From: Lucas Stach <l.stach@pengutronix.de>
+Date: Tue, 5 Apr 2022 21:18:30 +0200
+Subject: [PATCH 04/11] dt-bindings: display: imx: add binding for i.MX8MP HDMI
+ PVI
+
+Add binding for the i.MX8MP HDMI parallel video interface block.
+
+Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
+Tested-by: Marek Vasut <marex@denx.de>
+---
+ .../display/imx/fsl,imx8mp-hdmi-pvi.yaml      | 83 +++++++++++++++++++
+ 1 file changed, 83 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml
+
+diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml
+new file mode 100644
+index 000000000000..bf25d29c03ab
+--- /dev/null
++++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi-pvi.yaml
+@@ -0,0 +1,83 @@
++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/display/imx/fsl,imx8mp-hdmi-pvi.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Freescale i.MX8MP HDMI Parallel Video Interface
++
++maintainers:
++  - Lucas Stach <l.stach@pengutronix.de>
++
++description: |
++  The HDMI parallel video interface is timing and sync generator block in the
++  i.MX8MP SoC, that sits between the video source and the HDMI TX controller.
++
++properties:
++  compatible:
++    enum:
++      - fsl,imx8mp-hdmi-pvi
++
++  reg:
++    maxItems: 1
++
++  power-domains:
++    maxItems: 1
++
++  ports:
++    $ref: /schemas/graph.yaml#/properties/ports
++    description: |
++      This device has two video ports.
++
++    properties:
++      port@0:
++        $ref: /schemas/graph.yaml#/properties/port
++        description: Input from the LCDIF controller.
++
++      port@1:
++        $ref: /schemas/graph.yaml#/properties/port
++        description: Output to the HDMI TX controller
++
++    anyOf:
++      - required:
++          - port@0
++      - required:
++          - port@1
++
++required:
++  - compatible
++  - reg
++  - power-domains
++  - ports
++
++additionalProperties: false
++
++examples:
++  - |
++    #include <dt-bindings/clock/imx8mp-clock.h>
++    #include <dt-bindings/power/imx8mp-power.h>
++
++    display-bridge@32fc4000 {
++        compatible = "fsl,imx8mp-hdmi-pvi";
++        reg = <0x32fc4000 0x40>;
++        power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>;
++
++        ports {
++            #address-cells = <1>;
++            #size-cells = <0>;
++
++            port@0 {
++                reg = <0>;
++                pvi_from_lcdif3: endpoint {
++                    remote-endpoint = <&lcdif3_to_pvi>;
++                };
++            };
++
++            port@1 {
++                reg = <1>;
++                pvi_to_hdmi_tx: endpoint {
++                    remote-endpoint = <&hdmi_tx_from_pvi>;
++                };
++            };
++        };
++    };
+-- 
+2.40.0
+

linux/patches6.7/imx8mp-mnt-pocket-reform/hdmi/0005-drm-imx-add-driver-for-HDMI-TX-Parallel-Video-Interf.patch

+From 7a0a27bc5419b48b20b7a18b555bd33ae20a5c52 Mon Sep 17 00:00:00 2001
+From: Lucas Stach <l.stach@pengutronix.de>
+Date: Mon, 4 Apr 2022 19:18:30 +0200
+Subject: [PATCH 05/11] drm/imx: add driver for HDMI TX Parallel Video
+ Interface
+
+This IP block is found in the HDMI subsystem of the i.MX8MP SoC. It has a
+full timing generator and can switch between different video sources. On
+the i.MX8MP however the only supported source is the LCDIF. The block
+just needs to be powered up and told about the polarity of the video
+sync signals to act in bypass mode.
+
+Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
+Tested-by: Marek Vasut <marex@denx.de>
+---
+ drivers/gpu/drm/bridge/imx/Kconfig           |   7 +
+ drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c | 201 +++++++++++++++++++
+ 2 files changed, 208 insertions(+)
+ create mode 100644 drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c
+
+--- a/drivers/gpu/drm/bridge/imx/Kconfig
++++ b/drivers/gpu/drm/bridge/imx/Kconfig
+@@ -60,4 +60,11 @@ config DRM_IMX93_MIPI_DSI
+ 	  Choose this to enable MIPI DSI controller found in Freescale i.MX93
+ 	  processor.
+ 
++config DRM_IMX8MP_HDMI_PVI
++	tristate "i.MX8MP HDMI PVI bridge support"
++	depends on OF
++	help
++	  Choose this to enable support for the internal HDMI TX Parallel
++	  Video Interface found on the i.MX8MP SoC.
++
+ endif # ARCH_MXC || COMPILE_TEST
+--- /dev/null
++++ b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pvi.c
+@@ -0,0 +1,201 @@
++// SPDX-License-Identifier: GPL-2.0+
++
++/*
++ * Copyright (C) 2022 Pengutronix, Lucas Stach <kernel@pengutronix.de>
++ */
++
++#include <drm/drm_atomic_helper.h>
++#include <drm/drm_bridge.h>
++#include <drm/drm_crtc.h>
++#include <linux/module.h>
++#include <linux/of_device.h>
++#include <linux/of_graph.h>
++#include <linux/pm_runtime.h>
++
++#define HTX_PVI_CTL	0x0
++#define  PVI_CTL_OP_VSYNC_POL	BIT(18)
++#define  PVI_CTL_OP_HSYNC_POL	BIT(17)
++#define  PVI_CTL_OP_DE_POL	BIT(16)
++#define  PVI_CTL_INP_VSYNC_POL	BIT(14)
++#define  PVI_CTL_INP_HSYNC_POL	BIT(13)
++#define  PVI_CTL_INP_DE_POL	BIT(12)
++#define  PVI_CTL_INPUT_LCDIF	BIT(2)
++#define  PVI_CTL_EN		BIT(0)
++
++struct imx_hdmi_pvi {
++	struct drm_bridge	bridge;
++	struct device		*dev;
++	struct drm_bridge	*next_bridge;
++	void __iomem		*regs;
++};
++
++static inline struct imx_hdmi_pvi *
++to_imx_hdmi_pvi(struct drm_bridge *bridge)
++{
++	return container_of(bridge, struct imx_hdmi_pvi, bridge);
++}
++
++static int imx_hdmi_pvi_bridge_attach(struct drm_bridge *bridge,
++				enum drm_bridge_attach_flags flags)
++{
++	struct imx_hdmi_pvi *pvi = to_imx_hdmi_pvi(bridge);
++
++	return drm_bridge_attach(bridge->encoder, pvi->next_bridge, bridge, flags);
++}
++
++static void imx_hdmi_pvi_bridge_enable(struct drm_bridge *bridge,
++				       struct drm_bridge_state *bridge_state)
++{
++	struct drm_atomic_state *state = bridge_state->base.state;
++	struct imx_hdmi_pvi *pvi = to_imx_hdmi_pvi(bridge);
++	struct drm_connector_state *conn_state;
++	const struct drm_display_mode *mode;
++	struct drm_crtc_state *crtc_state;
++	struct drm_connector *connector;
++	u32 bus_flags, val;
++
++	connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
++	conn_state = drm_atomic_get_new_connector_state(state, connector);
++	crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
++
++	if (WARN_ON(pm_runtime_resume_and_get(pvi->dev)))
++		return;
++
++	mode = &crtc_state->adjusted_mode;
++
++	val = PVI_CTL_INPUT_LCDIF;
++
++	if (mode->flags & DRM_MODE_FLAG_PVSYNC)
++		val |= PVI_CTL_OP_VSYNC_POL | PVI_CTL_INP_VSYNC_POL;
++
++	if (mode->flags & DRM_MODE_FLAG_PHSYNC)
++		val |= PVI_CTL_OP_HSYNC_POL | PVI_CTL_INP_HSYNC_POL;
++
++	if (pvi->next_bridge->timings)
++		bus_flags = pvi->next_bridge->timings->input_bus_flags;
++	else if (bridge_state)
++		bus_flags = bridge_state->input_bus_cfg.flags;
++
++	if (bus_flags & DRM_BUS_FLAG_DE_HIGH)
++		val |= PVI_CTL_OP_DE_POL | PVI_CTL_INP_DE_POL;
++
++	writel(val, pvi->regs + HTX_PVI_CTL);
++	val |= PVI_CTL_EN;
++	writel(val, pvi->regs + HTX_PVI_CTL);
++}
++
++static void imx_hdmi_pvi_bridge_disable(struct drm_bridge *bridge,
++					struct drm_bridge_state *bridge_state)
++{
++	struct imx_hdmi_pvi *pvi = to_imx_hdmi_pvi(bridge);
++
++	writel(0x0, pvi->regs + HTX_PVI_CTL);
++
++	pm_runtime_put(pvi->dev);
++}
++
++static u32 *pvi_bridge_get_input_bus_fmts(struct drm_bridge *bridge,
++					  struct drm_bridge_state *bridge_state,
++					  struct drm_crtc_state *crtc_state,
++					  struct drm_connector_state *conn_state,
++					  u32 output_fmt,
++					  unsigned int *num_input_fmts)
++{
++	struct imx_hdmi_pvi *pvi = to_imx_hdmi_pvi(bridge);
++	struct drm_bridge *next_bridge = pvi->next_bridge;
++	struct drm_bridge_state *next_state;
++
++	if (!next_bridge->funcs->atomic_get_input_bus_fmts)
++		return 0;
++
++	next_state = drm_atomic_get_new_bridge_state(crtc_state->state,
++						     next_bridge);
++
++	return next_bridge->funcs->atomic_get_input_bus_fmts(next_bridge,
++							     next_state,
++							     crtc_state,
++							     conn_state,
++							     output_fmt,
++							     num_input_fmts);
++}
++
++static const struct drm_bridge_funcs imx_hdmi_pvi_bridge_funcs = {
++	.attach		= imx_hdmi_pvi_bridge_attach,
++	.atomic_enable	= imx_hdmi_pvi_bridge_enable,
++	.atomic_disable	= imx_hdmi_pvi_bridge_disable,
++	.atomic_get_input_bus_fmts = pvi_bridge_get_input_bus_fmts,
++	.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
++	.atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
++	.atomic_reset = drm_atomic_helper_bridge_reset,
++};
++
++static int imx_hdmi_pvi_probe(struct platform_device *pdev)
++{
++	struct device_node *remote;
++	struct imx_hdmi_pvi *pvi;
++
++	pvi = devm_kzalloc(&pdev->dev, sizeof(*pvi), GFP_KERNEL);
++	if (!pvi)
++		return -ENOMEM;
++
++	platform_set_drvdata(pdev, pvi);
++	pvi->dev = &pdev->dev;
++
++	pvi->regs = devm_platform_ioremap_resource(pdev, 0);
++	if (IS_ERR(pvi->regs))
++		return PTR_ERR(pvi->regs);
++
++	/* Get the next bridge in the pipeline. */
++	remote = of_graph_get_remote_node(pdev->dev.of_node, 1, -1);
++	if (!remote)
++		return -EINVAL;
++
++	pvi->next_bridge = of_drm_find_bridge(remote);
++	of_node_put(remote);
++
++	if (!pvi->next_bridge)
++		return dev_err_probe(&pdev->dev, -EPROBE_DEFER,
++				     "could not find next bridge\n");
++
++	/* Register the bridge. */
++	pvi->bridge.funcs = &imx_hdmi_pvi_bridge_funcs;
++	pvi->bridge.of_node = pdev->dev.of_node;
++	pvi->bridge.timings = pvi->next_bridge->timings;
++
++	drm_bridge_add(&pvi->bridge);
++
++	pm_runtime_enable(&pdev->dev);
++
++	return 0;
++}
++
++static int imx_hdmi_pvi_remove(struct platform_device *pdev)
++{
++	struct imx_hdmi_pvi *pvi = platform_get_drvdata(pdev);
++
++	drm_bridge_remove(&pvi->bridge);
++
++	return 0;
++}
++
++static const struct of_device_id imx_hdmi_pvi_match[] = {
++	{
++		.compatible = "fsl,imx8mp-hdmi-pvi",
++	}, {
++		/* sentinel */
++	},
++};
++MODULE_DEVICE_TABLE(of, imx_hdmi_pvi_match);
++
++static struct platform_driver imx_hdmi_pvi_driver = {
++	.probe	= imx_hdmi_pvi_probe,
++	.remove	= imx_hdmi_pvi_remove,
++	.driver		= {
++		.name = "imx-hdmi-pvi",
++		.of_match_table	= imx_hdmi_pvi_match,
++	},
++};
++module_platform_driver(imx_hdmi_pvi_driver);
++
++MODULE_DESCRIPTION("i.MX8MP HDMI TX Parallel Video Interface bridge driver");
++MODULE_LICENSE("GPL");

linux/patches6.7/imx8mp-mnt-pocket-reform/hdmi/0006-arm64-dts-imx8mp-add-HDMI-irqsteer.patch

+From 613178332bc0953c9593fab7f2526c86ae6d8d35 Mon Sep 17 00:00:00 2001
+From: Lucas Stach <l.stach@pengutronix.de>
+Date: Wed, 30 Mar 2022 18:41:09 +0200
+Subject: [PATCH 06/11] arm64: dts: imx8mp: add HDMI irqsteer
+
+The HDMI irqsteer is a secondary interrupt controller within the HDMI
+subsystem that maps all HDMI peripheral IRQs into a single upstream
+IRQ line.
+
+Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
+---
+ arch/arm64/boot/dts/freescale/imx8mp.dtsi | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
++++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+@@ -1357,6 +1357,19 @@
+ 				intf_mode = <&gpr 0x4>;
+ 				status = "disabled";
+ 			};
++
++			irqsteer_hdmi: interrupt-controller@32fc2000 {
++				compatible = "fsl,imx-irqsteer";
++				reg = <0x32fc2000 0x44>;
++				interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
++				interrupt-controller;
++				#interrupt-cells = <1>;
++				fsl,channel = <1>;
++				fsl,num-irqs = <64>;
++				clocks = <&clk IMX8MP_CLK_HDMI_APB>;
++				clock-names = "ipg";
++				power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_IRQSTEER>;
++			};
+ 		};
+ 
+ 		aips5: bus@30c00000 {

linux/patches6.7/imx8mp-mnt-pocket-reform/hdmi/0007-dt-bindings-display-imx-add-binding-for-i.MX8MP-HDMI.patch

+From 6f262cac5afa2366d1ab78b95c23076a18f68d7c Mon Sep 17 00:00:00 2001
+From: Lucas Stach <l.stach@pengutronix.de>
+Date: Tue, 5 Apr 2022 21:09:13 +0200
+Subject: [PATCH 07/11] dt-bindings: display: imx: add binding for i.MX8MP HDMI
+ TX
+
+The HDMI TX controller on the i.MX8MP SoC is a Synopsys designware IP
+core with a little bit of SoC integration around it.
+
+Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
+Tested-by: Marek Vasut <marex@denx.de>
+---
+ .../bindings/display/imx/fsl,imx8mp-hdmi.yaml | 74 +++++++++++++++++++
+ 1 file changed, 74 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.yaml
+
+diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.yaml
+new file mode 100644
+index 000000000000..14f7cd47209c
+--- /dev/null
++++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8mp-hdmi.yaml
+@@ -0,0 +1,74 @@
++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/display/imx/fsl,imx8mp-hdmi.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Freescale i.MX8MP DWC HDMI TX Encoder
++
++maintainers:
++  - Lucas Stach <l.stach@pengutronix.de>
++
++description: |
++  The HDMI transmitter is a Synopsys DesignWare HDMI 2.0 TX controller IP.
++
++allOf:
++  - $ref: ../bridge/synopsys,dw-hdmi.yaml#
++
++properties:
++  compatible:
++    enum:
++      - fsl,imx8mp-hdmi
++
++  reg:
++    maxItems: 1
++
++  reg-io-width:
++    const: 1
++
++  clocks:
++    maxItems: 5
++
++  clock-names:
++    items:
++      - {}
++      - {}
++      - const: cec
++      - const: pix
++      - const: fdcc
++
++  interrupts:
++    maxItems: 1
++
++  power-domains:
++    maxItems: 1
++
++required:
++  - compatible
++  - reg
++  - clocks
++  - clock-names
++  - interrupts
++  - power-domains
++
++additionalProperties: false
++
++examples:
++  - |
++    #include <dt-bindings/interrupt-controller/irq.h>
++    #include <dt-bindings/clock/imx8mp-clock.h>
++    #include <dt-bindings/power/imx8mp-power.h>
++
++    hdmi@32fd8000 {
++        compatible = "fsl,imx8mp-hdmi";
++        reg = <0x32fd8000 0x7eff>;
++        interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
++        clocks = <&clk IMX8MP_CLK_HDMI_APB>,
++                 <&clk IMX8MP_CLK_HDMI_REF_266M>,
++                 <&clk IMX8MP_CLK_HDMI_FDCC_TST>,
++                 <&clk IMX8MP_CLK_32K>,
++                 <&hdmi_tx_phy>;
++        clock-names = "iahb", "isfr", "fdcc", "cec", "pix";
++        power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>;
++        reg-io-width = <1>;
++    };
+-- 
+2.40.0
+

linux/patches6.7/imx8mp-mnt-pocket-reform/hdmi/0008-drm-imx-add-bridge-wrapper-driver-for-i.MX8MP-DWC-HD.patch

+From 854ae91ceec110b553302ba5954996e0ca3996a3 Mon Sep 17 00:00:00 2001
+From: Lucas Stach <l.stach@pengutronix.de>
+Date: Fri, 1 Apr 2022 22:11:44 +0200
+Subject: [PATCH 08/11] drm/imx: add bridge wrapper driver for i.MX8MP DWC HDMI
+
+Add a simple wrapper driver for the DWC HDMI bridge driver that
+implements the few bits that are necessary to abstract the i.MX8MP
+SoC integration.
+
+Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
+Tested-by: Marek Vasut <marex@denx.de>
+---
+ drivers/gpu/drm/bridge/imx/Kconfig       |   9 ++
+ drivers/gpu/drm/bridge/imx/imx8mp-hdmi.c | 141 +++++++++++++++++++++++
+ 2 files changed, 150 insertions(+)
+ create mode 100644 drivers/gpu/drm/bridge/imx/imx8mp-hdmi.c
+
+--- a/drivers/gpu/drm/bridge/imx/Kconfig
++++ b/drivers/gpu/drm/bridge/imx/Kconfig
+@@ -67,4 +67,13 @@ config DRM_IMX8MP_HDMI_PVI
+ 	  Choose this to enable support for the internal HDMI TX Parallel
+ 	  Video Interface found on the i.MX8MP SoC.
+ 
++config DRM_IMX8MP_DW_HDMI_BRIDGE
++	tristate "i.MX8MP HDMI bridge support"
++	depends on OF
++	depends on COMMON_CLK
++	select DRM_DW_HDMI
++	help
++	  Choose this to enable support for the internal HDMI encoder found
++	  on the i.MX8MP SoC.
++
+ endif # ARCH_MXC || COMPILE_TEST
+--- /dev/null
++++ b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi.c
+@@ -0,0 +1,141 @@
++// SPDX-License-Identifier: GPL-2.0+
++
++/*
++ * Copyright (C) 2022 Pengutronix, Lucas Stach <kernel@pengutronix.de>
++ */
++
++#include <drm/bridge/dw_hdmi.h>
++#include <drm/drm_modes.h>
++#include <linux/clk.h>
++#include <linux/mod_devicetable.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++
++struct imx_hdmi {
++	struct dw_hdmi_plat_data plat_data;
++	struct dw_hdmi *dw_hdmi;
++	struct clk *pixclk;
++	struct clk *fdcc;
++};
++
++static enum drm_mode_status
++imx8mp_hdmi_mode_valid(struct dw_hdmi *dw_hdmi, void *data,
++		       const struct drm_display_info *info,
++		       const struct drm_display_mode *mode)
++{
++	struct imx_hdmi *hdmi = (struct imx_hdmi *)data;
++
++	if (mode->clock < 13500)
++		return MODE_CLOCK_LOW;
++
++	if (mode->clock > 297000)
++		return MODE_CLOCK_HIGH;
++
++	if (clk_round_rate(hdmi->pixclk, mode->clock * 1000) !=
++	    mode->clock * 1000)
++		return MODE_CLOCK_RANGE;
++
++	/* We don't support double-clocked and Interlaced modes */
++	if ((mode->flags & DRM_MODE_FLAG_DBLCLK) ||
++	    (mode->flags & DRM_MODE_FLAG_INTERLACE))
++		return MODE_BAD;
++
++	return MODE_OK;
++}
++
++static int imx8mp_hdmi_phy_init(struct dw_hdmi *dw_hdmi, void *data,
++				const struct drm_display_info *display,
++				const struct drm_display_mode *mode)
++{
++	return 0;
++}
++
++static void imx8mp_hdmi_phy_disable(struct dw_hdmi *dw_hdmi, void *data)
++{
++}
++
++static const struct dw_hdmi_phy_ops imx8mp_hdmi_phy_ops = {
++	.init		= imx8mp_hdmi_phy_init,
++	.disable	= imx8mp_hdmi_phy_disable,
++	.read_hpd	= dw_hdmi_phy_read_hpd,
++	.update_hpd	= dw_hdmi_phy_update_hpd,
++	.setup_hpd	= dw_hdmi_phy_setup_hpd,
++};
++
++static int imx_dw_hdmi_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct dw_hdmi_plat_data *plat_data;
++	struct imx_hdmi *hdmi;
++	int ret;
++
++	hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
++	if (!hdmi)
++		return -ENOMEM;
++
++	plat_data = &hdmi->plat_data;
++
++	hdmi->pixclk = devm_clk_get(dev, "pix");
++	if (IS_ERR(hdmi->pixclk))
++		return dev_err_probe(dev, PTR_ERR(hdmi->pixclk),
++				     "Unable to get pixel clock\n");
++
++	hdmi->fdcc = devm_clk_get(dev, "fdcc");
++	if (IS_ERR(hdmi->fdcc))
++		return dev_err_probe(dev, PTR_ERR(hdmi->fdcc),
++				     "Unable to get FDCC clock\n");
++
++	ret = clk_prepare_enable(hdmi->fdcc);
++	if (ret)
++		return dev_err_probe(dev, ret, "Unable to enable FDCC clock\n");
++
++	plat_data->mode_valid = imx8mp_hdmi_mode_valid;
++	plat_data->phy_ops = &imx8mp_hdmi_phy_ops;
++	plat_data->phy_name = "SAMSUNG HDMI TX PHY";
++	plat_data->priv_data = hdmi;
++
++	hdmi->dw_hdmi = dw_hdmi_probe(pdev, plat_data);
++	if (IS_ERR(hdmi->dw_hdmi))
++		return PTR_ERR(hdmi->dw_hdmi);
++
++	/*
++	 * Just release PHY core from reset, all other power management is done
++	 * by the PHY driver.
++	 */
++	dw_hdmi_phy_gen1_reset(hdmi->dw_hdmi);
++
++	platform_set_drvdata(pdev, hdmi);
++
++	return 0;
++}
++
++static int imx_dw_hdmi_remove(struct platform_device *pdev)
++{
++	struct imx_hdmi *hdmi = platform_get_drvdata(pdev);
++
++	dw_hdmi_remove(hdmi->dw_hdmi);
++
++	clk_disable_unprepare(hdmi->fdcc);
++
++	return 0;
++}
++
++static const struct of_device_id imx_dw_hdmi_of_table[] = {
++	{ .compatible = "fsl,imx8mp-hdmi" },
++	{ /* Sentinel */ },
++};
++MODULE_DEVICE_TABLE(of, imx_dw_hdmi_of_table);
++
++static struct platform_driver im_dw_hdmi_platform_driver = {
++	.probe		= imx_dw_hdmi_probe,
++	.remove		= imx_dw_hdmi_remove,
++	.driver		= {
++		.name	= "imx-dw-hdmi",
++		.of_match_table = imx_dw_hdmi_of_table,
++	},
++};
++
++module_platform_driver(im_dw_hdmi_platform_driver);
++
++MODULE_DESCRIPTION("i.MX8M HDMI encoder driver");
++MODULE_LICENSE("GPL");

linux/patches6.7/imx8mp-mnt-pocket-reform/hdmi/0009-dt-bindings-phy-add-binding-for-the-i.MX8MP-HDMI-PHY.patch

+From 73c43eb4b3bff11a47a6829aad3173c8007c18a2 Mon Sep 17 00:00:00 2001
+From: Lucas Stach <l.stach@pengutronix.de>
+Date: Tue, 5 Apr 2022 20:54:27 +0200
+Subject: [PATCH 09/11] dt-bindings: phy: add binding for the i.MX8MP HDMI PHY
+
+Add a DT binding for the HDMI PHY found on the i.MX8MP SoC.
+
+Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
+Tested-by: Marek Vasut <marex@denx.de>
+---
+ .../bindings/phy/fsl,imx8mp-hdmi-phy.yaml     | 62 +++++++++++++++++++
+ 1 file changed, 62 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml
+
+diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml
+new file mode 100644
+index 000000000000..bc21c073e92a
+--- /dev/null
++++ b/Documentation/devicetree/bindings/phy/fsl,imx8mp-hdmi-phy.yaml
+@@ -0,0 +1,62 @@
++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/phy/fsl,imx8mp-hdmi-phy.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Freescale i.MX8MP HDMI PHY binding
++
++maintainers:
++  - Lucas Stach <l.stach@pengutronix.de>
++
++properties:
++  compatible:
++    enum:
++      - fsl,imx8mp-hdmi-phy
++
++  reg:
++    maxItems: 1
++
++  "#clock-cells":
++    const: 0
++
++  clocks:
++    minItems: 2
++    maxItems: 2
++
++  clock-names:
++    items:
++      - const: apb
++      - const: ref
++
++  "#phy-cells":
++    const: 0
++
++  power-domains:
++    maxItems: 1
++
++required:
++  - compatible
++  - reg
++  - "#clock-cells"
++  - clocks
++  - clock-names
++  - power-domains
++
++additionalProperties: false
++
++examples:
++  - |
++    #include <dt-bindings/clock/imx8mp-clock.h>
++    #include <dt-bindings/power/imx8mp-power.h>
++
++    phy@32fdff00 {
++        compatible = "fsl,imx8mp-hdmi-phy";
++        reg = <0x32fdff00 0x100>;
++        clocks = <&clk IMX8MP_CLK_HDMI_APB>,
++                 <&clk IMX8MP_CLK_HDMI_24M>;
++        clock-names = "apb", "ref";
++        power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>;
++        #clock-cells = <0>;
++        #phy-cells = <0>;
++    };
+-- 
+2.40.0
+

linux/patches6.7/imx8mp-mnt-pocket-reform/hdmi/0010-arm64-dts-imx8mp-add-HDMI-power-domains.patch

+From d1f84163b33b4fed1a4638f5d51abefc5fe0ac25 Mon Sep 17 00:00:00 2001
+From: Lucas Stach <l.stach@pengutronix.de>
+Date: Wed, 30 Mar 2022 18:24:43 +0200
+Subject: [PATCH 10/11] arm64: dts: imx8mp: add HDMI power-domains
+
+This adds the PGC and HDMI blk-ctrl nodes providing power control for
+HDMI subsystem peripherals.
+
+Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
+---
+ arch/arm64/boot/dts/freescale/imx8mp.dtsi | 35 +++++++++++++++++++++++
+ 1 file changed, 35 insertions(+)
+
+--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
++++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+@@ -841,6 +841,23 @@
+ 							 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
+ 					};
+ 
++					pgc_hdmimix: power-domains@14 {
++						#power-domain-cells = <0>;
++						reg = <IMX8MP_POWER_DOMAIN_HDMIMIX>;
++						clocks = <&clk IMX8MP_CLK_HDMI_ROOT>,
++							 <&clk IMX8MP_CLK_HDMI_APB>;
++						assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>,
++								  <&clk IMX8MP_CLK_HDMI_APB>;
++						assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>,
++									 <&clk IMX8MP_SYS_PLL1_133M>;
++						assigned-clock-rates = <500000000>, <133000000>;
++					};
++
++					pgc_hdmi_phy: power-domains@15 {
++						#power-domain-cells = <0>;
++						reg = <IMX8MP_POWER_DOMAIN_HDMI_PHY>;
++					};
++
+ 					pgc_mipi_phy2: power-domain@16 {
+ 						#power-domain-cells = <0>;
+ 						reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
+@@ -1370,6 +1387,24 @@
+ 				clock-names = "ipg";
+ 				power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_IRQSTEER>;
+ 			};
++
++			hdmi_blk_ctrl: blk-ctrl@32fc0000 {
++				compatible = "fsl,imx8mp-hdmi-blk-ctrl", "syscon";
++				reg = <0x32fc0000 0x23c>;
++				clocks = <&clk IMX8MP_CLK_HDMI_APB>,
++					 <&clk IMX8MP_CLK_HDMI_ROOT>,
++					 <&clk IMX8MP_CLK_HDMI_REF_266M>,
++					 <&clk IMX8MP_CLK_HDMI_24M>;
++				clock-names = "apb", "axi", "ref_266m", "ref_24m";
++				power-domains = <&pgc_hdmimix>, <&pgc_hdmimix>,
++						<&pgc_hdmimix>, <&pgc_hdmimix>,
++						<&pgc_hdmimix>, <&pgc_hdmimix>,
++						<&pgc_hdmimix>, <&pgc_hdmi_phy>;
++				power-domain-names = "bus", "irqsteer", "lcdif",
++						     "pai", "pvi", "trng",
++						     "hdmi-tx", "hdmi-tx-phy";
++				#power-domain-cells = <1>;
++			};
+ 		};
+ 
+ 		aips5: bus@30c00000 {

linux/patches6.7/imx8mp-mnt-pocket-reform/hdmi/0011-hdmi-pvi-makefile.patch

+From df862bd710dd94cea3848176dc13e30ba3d87fbd Mon Sep 17 00:00:00 2001
+From: "Lukas F. Hartmann" <lukas@mntre.com>
+Date: Sun, 9 Jul 2023 22:14:11 +0200
+Subject: [PATCH 11/11] hdmi-pvi-makefile
+
+---
+ drivers/gpu/drm/bridge/imx/Makefile | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/gpu/drm/bridge/imx/Makefile
++++ b/drivers/gpu/drm/bridge/imx/Makefile
+@@ -5,3 +5,6 @@ obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER)
+ obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o
+ obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI) += imx8qxp-pxl2dpi.o
+ obj-$(CONFIG_DRM_IMX93_MIPI_DSI) += imx93-mipi-dsi.o
++
++obj-$(CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE) += imx8mp-hdmi.o
++obj-$(CONFIG_DRM_IMX8MP_HDMI_PVI) += imx8mp-hdmi-pvi.o

linux/patches6.7/imx8mp-mnt-pocket-reform/mmc-sdio/0001-sdhci-add-no-sd-uhs-sdr104-devicetree-property.patch

+From 9f11ce621bccb07064ccc9c564fb0cb20612e1cd Mon Sep 17 00:00:00 2001
+From: Troy Kisky <troy.kisky@boundarydevices.com>
+Date: Fri, 1 Dec 2017 18:32:51 -0700
+Subject: [PATCH 1/3] sdhci: add no-sd-uhs-sdr104 devicetree property
+
+Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
+---
+ drivers/mmc/host/sdhci.c | 18 +++++++++++++-----
+ 1 file changed, 13 insertions(+), 5 deletions(-)
+
+--- a/drivers/mmc/host/sdhci.c
++++ b/drivers/mmc/host/sdhci.c
+@@ -16,6 +16,7 @@
+ #include <linux/highmem.h>
+ #include <linux/io.h>
+ #include <linux/module.h>
++#include <linux/of.h>
+ #include <linux/dma-mapping.h>
+ #include <linux/slab.h>
+ #include <linux/scatterlist.h>
+@@ -4550,12 +4551,19 @@ int sdhci_setup_host(struct sdhci_host *
+ 
+ 	/* SDR104 supports also implies SDR50 support */
+ 	if (host->caps1 & SDHCI_SUPPORT_SDR104) {
++		struct device_node *np;
++
+ 		mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
+-		/* SD3.0: SDR104 is supported so (for eMMC) the caps2
+-		 * field can be promoted to support HS200.
+-		 */
+-		if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
+-			mmc->caps2 |= MMC_CAP2_HS200;
++		np = mmc->parent->of_node;
++		if (of_property_read_bool(np, "no-sd-uhs-sdr104")) {
++			mmc->caps &= ~MMC_CAP_UHS_SDR104;
++		} else {
++			/* SD3.0: SDR104 is supported so (for eMMC) the caps2
++			 * field can be promoted to support HS200.
++			 */
++			if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
++				mmc->caps2 |= MMC_CAP2_HS200;
++		}
+ 	} else if (host->caps1 & SDHCI_SUPPORT_SDR50) {
+ 		mmc->caps |= MMC_CAP_UHS_SDR50;
+ 	}

linux/patches6.7/imx8mp-mnt-pocket-reform/mmc-sdio/0002-During-the-card-init-the-host-side-sometimes-may-nee.patch

+From 59e34fd41e32a11bd05494c44402ff202ef9e570 Mon Sep 17 00:00:00 2001
+From: Haibo Chen <haibo.chen@xxxxxxx>
+Date: Sun, 9 Jul 2023 22:16:01 +0200
+Subject: [PATCH 2/3] During the card init, the host side sometimes may need to
+ distinguish the card type to handle accordingly. So need to give host->card
+ value earlier.
+
+Signed-off-by: Haibo Chen <haibo.chen@xxxxxxx>
+---
+ drivers/mmc/core/mmc.c  |  9 +++++----
+ drivers/mmc/core/sd.c   |  7 +++++--
+ drivers/mmc/core/sdio.c | 10 ++++++----
+ 3 files changed, 16 insertions(+), 10 deletions(-)
+
+--- a/drivers/mmc/core/mmc.c
++++ b/drivers/mmc/core/mmc.c
+@@ -1657,6 +1657,8 @@ static int mmc_init_card(struct mmc_host
+ 			goto err;
+ 		}
+ 
++		host->card = card;
++
+ 		card->ocr = ocr;
+ 		card->type = MMC_TYPE_MMC;
+ 		card->rca = 1;
+@@ -1931,14 +1933,13 @@ static int mmc_init_card(struct mmc_host
+ 		goto free_card;
+ 	}
+ 
+-	if (!oldcard)
+-		host->card = card;
+-
+ 	return 0;
+ 
+ free_card:
+-	if (!oldcard)
++	if (!oldcard) {
+ 		mmc_remove_card(card);
++		host->card = NULL;
++	}
+ err:
+ 	return err;
+ }
+--- a/drivers/mmc/core/sd.c
++++ b/drivers/mmc/core/sd.c
+@@ -1431,6 +1431,8 @@ retry:
+ 		if (IS_ERR(card))
+ 			return PTR_ERR(card);
+ 
++		host->card = card;
++
+ 		card->ocr = ocr;
+ 		card->type = MMC_TYPE_SD;
+ 		memcpy(card->raw_cid, cid, sizeof(card->raw_cid));
+@@ -1577,12 +1579,13 @@ cont:
+ 		goto free_card;
+ 	}
+ 
+-	host->card = card;
+ 	return 0;
+ 
+ free_card:
+-	if (!oldcard)
++	if (!oldcard) {
+ 		mmc_remove_card(card);
++		host->card = NULL;
++	}
+ 
+ 	return err;
+ }
+--- a/drivers/mmc/core/sdio.c
++++ b/drivers/mmc/core/sdio.c
+@@ -699,6 +699,9 @@ try_again:
+ 	if (IS_ERR(card))
+ 		return PTR_ERR(card);
+ 
++	if (!oldcard)
++		host->card = card;
++
+ 	if ((rocr & R4_MEMORY_PRESENT) &&
+ 	    mmc_sd_get_cid(host, ocr & rocr, card->raw_cid, NULL) == 0) {
+ 		card->type = MMC_TYPE_SD_COMBO;
+@@ -800,8 +803,6 @@ try_again:
+ 
+ 		if (oldcard)
+ 			mmc_remove_card(card);
+-		else
+-			host->card = card;
+ 
+ 		return 0;
+ 	}
+@@ -898,14 +899,15 @@ try_again:
+ 		goto remove;
+ 	}
+ 
+-	host->card = card;
+ 	return 0;
+ 
+ mismatch:
+ 	pr_debug("%s: Perhaps the card was replaced\n", mmc_hostname(host));
+ remove:
+-	if (oldcard != card)
++	if (oldcard != card) {
+ 		mmc_remove_card(card);
++		host->card = NULL;
++	}
+ 	return err;
+ }
+ 

linux/patches6.7/imx8mp-mnt-pocket-reform/mmc-sdio/0003-USDHC-IP-has-one-limitation-the-tuning-circuit-can-t.patch

+From c39839e4da6c0a0f24ff2532a793b5829ce28e82 Mon Sep 17 00:00:00 2001
+From: Haibo Chen <haibo.chen@xxxxxxx>
+Date: Sun, 9 Jul 2023 22:16:02 +0200
+Subject: [PATCH 3/3] USDHC IP has one limitation: the tuning circuit can't
+ handle the async sdio device interrupt correctly. When sdio device use 4 data
+ lines, async sdio interrupt will use the shared DAT[1], if enable auto tuning
+ circuit to check these 4 data lines, include the DAT[1], this circuit will
+ detect this interrupt, take this as data on DAT[1], and adjust the delay cell
+ wrongly, finally will cause the DATA/CMD CRC error. So for SDIO device, only
+ enable DAT[0] and CMD line for auto tuning.
+
+Signed-off-by: Haibo Chen <haibo.chen@xxxxxxx>
+---
+ drivers/mmc/host/sdhci-esdhc-imx.c | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
+index 03fe21a89021..de7030a09711 100644
+--- a/drivers/mmc/host/sdhci-esdhc-imx.c
++++ b/drivers/mmc/host/sdhci-esdhc-imx.c
+@@ -475,6 +475,20 @@ static inline void usdhc_auto_tuning_mode_sel_and_en(struct sdhci_host *host)
+ 	if (imx_data->init_card_type == MMC_TYPE_SDIO)
+ 		auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_1BIT_EN;
+ 
++	/*
++	 * For USDHC, auto tuning circuit can not handle the async sdio
++	 * device interrupt correctly. When sdio device use 4 data lines,
++	 * async sdio interrupt will use the shared DAT[1], if enable auto
++	 * tuning circuit check these 4 data lines, include the DAT[1],
++	 * this circuit will detect this interrupt, take this as a data on
++	 * DAT[1], and adjust the delay cell wrongly.
++	 * This is the hardware design limitation, to avoid this, for sdio
++	 * device, config the auto tuning circuit only check DAT[0] and CMD
++	 * line.
++	 */
++	if (!host->mmc->card && mmc_card_sdio(host->mmc->card))
++		auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_1BIT_EN;
++
+ 	esdhc_clrset_le(host, ESDHC_VEND_SPEC2_AUTO_TUNE_MODE_MASK,
+ 			auto_tune_buswidth | ESDHC_VEND_SPEC2_AUTO_TUNE_CMD_EN,
+ 			ESDHC_VEND_SPEC2);
+-- 
+2.40.0
+