.gitlab-ci.yml

+image: debian:bullseye-slim
+
+build:
+  script: |
+    apt-get update
+    apt-get --yes install --no-install-recommends gcc-aarch64-linux-gnu build-essential bison flex device-tree-compiler git
+    cp mntreform-config .config
+    ./build.sh
+    if git describe >/dev/null 2>&1; then
+      grep --quiet --fixed-strings "EXTRAVERSION = \\ MNT\\ Reform\\ $(git describe --always --tags --abbrev=0)" Makefile
+    fi
+    mv flash.bin imx8mq-mnt-reform2-flash.bin
+    cp imx8mq-mnt-reform2-flash.bin imx8mq-mnt-reform2-hdmi-flash.bin
+  artifacts:
+    paths:
+      - "imx8mq-mnt-reform2-flash.bin"
+      - "imx8mq-mnt-reform2-hdmi-flash.bin"

Makefile

@@ -3,7 +3,7 @@
 VERSION = 2018
 PATCHLEVEL = 07
 SUBLEVEL =
-EXTRAVERSION =
+EXTRAVERSION = \ MNT\ Reform\ 2024-07-19
 NAME =
 
 # *DOCUMENTATION*
@@ -607,14 +607,18 @@ endif
 KBUILD_CFLAGS += $(call cc-option,-fno-stack-protector)
 KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks)
 
-# change __FILE__ to the relative path from the srctree
-KBUILD_CFLAGS	+= $(call cc-option,-fmacro-prefix-map=$(srctree)/=)
+# change __FILE__ and debugging symbols to the relative path from the
+# srctree
+KBUILD_CFLAGS	+= $(call cc-option,-ffile-prefix-map=$(srctree)/=)
 
 KBUILD_CFLAGS	+= -g
 # $(KBUILD_AFLAGS) sets -g, which causes gcc to pass a suitable -g<format>
 # option to the assembler.
 KBUILD_AFLAGS	+= -g
 
+# Use relative paths in debugging symbols
+KBUILD_AFLAGS   += --debug-prefix-map=$(srctree)/=
+
 # Report stack usage if supported
 # ARC tools based on GCC 7.1 has an issue with stack usage
 # with naked functions, see commit message for more details
@@ -1074,6 +1078,11 @@ SOC_CPU = iMX8MM
 TEE_LOAD_ADDR = 0xbe000000
 ATF_LOAD_ADDR = 0x00920000
 endif
+ifdef CONFIG_IMX8MN
+SOC_CPU = iMX8MN
+TEE_LOAD_ADDR = 0xbe000000
+ATF_LOAD_ADDR = 0x00960000
+endif
 ifdef CONFIG_IMX8MQ
 SOC_CPU = iMX8MQ
 TEE_LOAD_ADDR = 0xfe000000

README

@@ -2525,9 +2525,6 @@ FIT uImage format:
 		When defined, the linker checks that the actual size does
 		not exceed it.
 
-		CONFIG_SPL_TEXT_BASE
-		TEXT_BASE for linking the SPL binary.
-
 		CONFIG_SPL_RELOC_TEXT_BASE
 		Address to relocate to.  If unspecified, this is equal to
 		CONFIG_SPL_TEXT_BASE (i.e. no relocation is done).

arch/Kconfig

@@ -126,6 +126,7 @@ config X86
 	imply CMD_SF_TEST
 	imply CMD_ZBOOT
 	imply USB_HOST_ETHER
+	imply SPL_SYSRESET
 	imply USB_ETHER_ASIX
 	imply USB_ETHER_SMSC95XX
 

arch/arm/Kconfig

@@ -1254,6 +1254,7 @@ config ARCH_STM32MP
 	select SYSCON
 	select SYSRESET
 	select SYS_THUMB_BUILD
+	imply SPL_SYSRESET
 	help
 	  Support for STM32MP SoC family developed by STMicroelectronics,
 	  MPUs based on ARM cortex A core

arch/arm/dts/Makefile

@@ -438,7 +438,8 @@ dtb-$(CONFIG_MX7) += imx7-colibri.dtb \
 
 dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
 
-dtb-$(CONFIG_ARCH_IMX8M) += imx8mq-nitrogen8m.dtb \
+dtb-$(CONFIG_ARCH_IMX8M) += imx8mn-ddr4-evk.dtb \
+	imx8mq-nitrogen8m.dtb \
 	imx8mq-bio.dtb
 
 dtb-$(CONFIG_RCAR_GEN3) += \

arch/arm/dts/imx8mm-moo.dts

@@ -1075,14 +1075,13 @@
 };
 
 &usdhc1 {
+	cap-mmc-highspeed;
 	bus-width = <8>;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
 	no-mmc-hs400;
 	non-removable;
-#if 0
 	pinctrl-names = "default", "state_100mhz", "state_200mhz";
-#else
-	pinctrl-names = "default";
-#endif
 	pinctrl-0 = <&pinctrl_usdhc1>;
 	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
@@ -1095,11 +1094,16 @@
 
 &usdhc2 {
 	bus-width = <4>;
+	cap-sd-highspeed;
 	cd-gpios = GP_USDHC2_CD;
 	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 	pinctrl-0 = <&pinctrl_usdhc2>;
 	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
 	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+	sd-uhs-ddr50;
+	sd-uhs-sdr104;
+	sd-uhs-sdr12;
+	sd-uhs-sdr25;
 	status = "okay";
 #if 1
 	vqmmc-supply = <&reg_usdhc2_vqmmc>;

arch/arm/dts/imx8mm-nitrogen8mm.dts

@@ -1149,14 +1149,13 @@
 };
 
 &usdhc1 {
+	cap-mmc-highspeed;
 	bus-width = <8>;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
 	no-mmc-hs400;
 	non-removable;
-#if 0
 	pinctrl-names = "default", "state_100mhz", "state_200mhz";
-#else
-	pinctrl-names = "default";
-#endif
 	pinctrl-0 = <&pinctrl_usdhc1>;
 	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
@@ -1169,11 +1168,16 @@
 
 &usdhc2 {
 	bus-width = <4>;
+	cap-sd-highspeed;
 	cd-gpios = GP_USDHC2_CD;
 	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 	pinctrl-0 = <&pinctrl_usdhc2>;
 	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
 	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+	sd-uhs-ddr50;
+	sd-uhs-sdr104;
+	sd-uhs-sdr12;
+	sd-uhs-sdr25;
 	status = "okay";
 #if 1
 	vqmmc-supply = <&reg_usdhc2_vqmmc>;

arch/arm/dts/imx8mm-nitrogen8mm_rev2.dts

+/*
+ * Copyright 2018 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "imx8mm-nitrogen8mm.dts"
+
+/ {
+	model = "Boundary Devices i.MX8MMini Nitrogen8MM Rev2";
+	compatible = "boundary,imx8mm-nitrogen8mm_rev2", "fsl,imx8mm";
+};
+
+&wdog1 {
+	/delete-property/ reset-gpios;
+};

arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi

+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+&{/soc@0} {
+	u-boot,dm-pre-reloc;
+	u-boot,dm-spl;
+};
+
+&clk {
+	u-boot,dm-spl;
+	u-boot,dm-pre-reloc;
+};
+
+&osc_24m {
+	u-boot,dm-spl;
+	u-boot,dm-pre-reloc;
+};
+
+&aips1 {
+	u-boot,dm-spl;
+	u-boot,dm-pre-reloc;
+};
+
+&aips2 {
+	u-boot,dm-spl;
+};
+
+&aips3 {
+	u-boot,dm-spl;
+};
+
+&iomuxc {
+	u-boot,dm-spl;
+};
+
+&pinctrl_reg_usdhc2_vmmc {
+	u-boot,dm-spl;
+};
+
+&pinctrl_uart2 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+	u-boot,dm-spl;
+};
+
+&gpio1 {
+	u-boot,dm-spl;
+};
+
+&gpio2 {
+	u-boot,dm-spl;
+};
+
+&gpio3 {
+	u-boot,dm-spl;
+};
+
+&gpio4 {
+	u-boot,dm-spl;
+};
+
+&gpio5 {
+	u-boot,dm-spl;
+};
+
+&uart2 {
+	u-boot,dm-spl;
+};
+
+&usdhc1 {
+	u-boot,dm-spl;
+};
+
+&usdhc2 {
+	u-boot,dm-spl;
+};
+
+&usdhc3 {
+	u-boot,dm-spl;
+};

arch/arm/dts/imx8mn-ddr4-evk.dts

+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8mn.dtsi"
+
+/ {
+	model = "NXP i.MX8MNano DDR4 EVK board";
+	compatible = "fsl,imx8mn-ddr4-evk", "fsl,imx8mn";
+
+	chosen {
+		stdout-path = &uart2;
+	};
+
+	reg_usdhc2_vmmc: regulator-usdhc2 {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+		regulator-name = "VSD_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+
+	pinctrl_fec1: fec1grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_ENET_MDC_ENET1_MDC		0x3
+			MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO	0x3
+			MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f
+			MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f
+			MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f
+			MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f
+			MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91
+			MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91
+			MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91
+			MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91
+			MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f
+			MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91
+			MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
+			MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
+			MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22	0x19
+		>;
+	};
+
+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
+		fsl,pins = <
+			MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
+		>;
+	};
+
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
+			MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
+		>;
+	};
+
+	pinctrl_usdhc2_gpio: usdhc2grpgpio {
+		fsl,pins = <
+			MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x1c4
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
+			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
+			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
+			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
+			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
+			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
+			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
+		>;
+	};
+
+	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+		fsl,pins = <
+			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
+			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
+			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
+			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
+			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
+			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
+			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
+		>;
+	};
+
+	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+		fsl,pins = <
+			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
+			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
+			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
+			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
+			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
+			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
+			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000190
+			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0
+			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0
+			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0
+			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
+			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0
+			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0
+			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0
+			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0
+			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0
+			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x190
+		>;
+	};
+
+	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+		fsl,pins = <
+			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000194
+			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
+			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4
+			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4
+			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4
+			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4
+			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4
+			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4
+			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4
+			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4
+			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x194
+		>;
+	};
+
+	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+		fsl,pins = <
+			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK		0x40000196
+			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
+			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6
+			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6
+			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6
+			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6
+			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6
+			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6
+			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6
+			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6
+			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x196
+		>;
+	};
+
+	pinctrl_wdog: wdoggrp {
+		fsl,pins = <
+			MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0xc6
+		>;
+	};
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethphy0>;
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+			at803x,led-act-blind-workaround;
+			at803x,eee-disabled;
+			at803x,vddio-1p8v;
+		};
+	};
+};
+
+&snvs_pwrkey {
+	status = "okay";
+};
+
+&uart2 { /* console */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+	bus-width = <4>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};

arch/arm/dts/imx8mq-bio.dts

@@ -1155,13 +1155,12 @@
 };
 
 &usdhc1 {
+	cap-mmc-highspeed;
 	bus-width = <8>;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
 	no-mmc-hs400;
-#if 0
-	pinctrl-names = "default";
-#else
 	pinctrl-names = "default", "state_100mhz", "state_200mhz";
-#endif
 	pinctrl-0 = <&pinctrl_usdhc1>;
 	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;

arch/arm/dts/imx8mq-nitrogen8m.dts

@@ -1338,13 +1338,12 @@
 };
 
 &usdhc1 {
+	cap-mmc-highspeed;
 	bus-width = <8>;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
 	no-mmc-hs400;
-#if 0
-	pinctrl-names = "default";
-#else
 	pinctrl-names = "default", "state_100mhz", "state_200mhz";
-#endif
 	pinctrl-0 = <&pinctrl_usdhc1>;
 	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;

arch/arm/dts/imx8mq-nitrogen8m_som.dts

@@ -310,13 +310,6 @@
 		>;
 	};
 
-	pinctrl_reg_wlan_vmmc: reg-wlan-vmmcgrp {
-		fsl,pins = <
-#define GP_REG_WLAN_VMMC	<&gpio3 20 GPIO_ACTIVE_HIGH>
-			MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20		0x16
-		>;
-	};
-
 	pinctrl_sai1: sai1grp {
 		fsl,pins = <
 			/* wm8960 */
@@ -406,12 +399,6 @@
 			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
 			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
 			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
-#if 0
-			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
-#else
-#define GP_EMMC_RESET		<&gpio2 10 GPIO_ACTIVE_LOW>
-			MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10		0x41
-#endif
 		>;
 	};
 
@@ -445,6 +432,7 @@
 		>;
 	};
 
+
 	pinctrl_usdhc2: usdhc2grp {
 		fsl,pins = <
 			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x03
@@ -453,8 +441,6 @@
 			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
 			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
 			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
-			/* Bluetooth slow clock */
-			MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K	0x03
 		>;
 	};
 
@@ -603,18 +589,6 @@
 		regulator-max-microvolt = <5000000>;
 	};
 
-	reg_wlan_vmmc: regulator-wlan-vmmc {
-		compatible = "regulator-fixed";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_reg_wlan_vmmc>;
-		regulator-name = "reg_wlan_vmmc";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		gpio = GP_REG_WLAN_VMMC;
-		startup-delay-us = <70000>;
-		enable-active-high;
-	};
-
 #if 0
 	sound-wm8960 {
 		compatible = "fsl,imx-audio-wm8960";
@@ -1330,7 +1304,10 @@
 };
 
 &usdhc1 {
+	cap-mmc-highspeed;
 	bus-width = <8>;
+	// mmc-ddr-1_8v;
+	// mmc-hs200-1_8v;
 	fsl,strobe-dll-delay-target = <5>;
 	fsl,tuning-start-tap = <63>;
 	fsl,tuning-step = <2>;
@@ -1345,7 +1322,6 @@
 	vqmmc-1-8-v;
 };
 
-#if 0
 &usdhc2 {
 	bus-width = <4>;
 	fsl,tuning-start-tap = <70>;
@@ -1359,15 +1335,9 @@
 	status = "okay";
 	tuning-delay = <32>;
 	tuning-mode = <1>;
-	vmmc-supply = <&reg_wlan_vmmc>;
-	vqmmc-1-8-v;
+	vmmc-supply = <&reg_vref_3v3>;
 };
 
-&vpu {
-	regulator-supply = <&reg_vref_0v9>;
-	status = "okay";
-};
-#endif
 
 &wdog1 {
 	pinctrl-names = "default";

arch/arm/include/asm/arch-imx/cpu.h

@@ -17,6 +17,7 @@
 #define MXC_CPU_MX6Q		0x63
 #define MXC_CPU_MX6UL		0x64
 #define MXC_CPU_MX6ULL		0x65
+#define MXC_CPU_MX6ULZ		0x6B
 #define MXC_CPU_MX6SOLO		0x66 /* dummy */
 #define MXC_CPU_MX6SLL		0x67
 #define MXC_CPU_MX6D		0x6A
@@ -26,7 +27,16 @@
 #define MXC_CPU_MX7D		0x72
 #define MXC_CPU_MX7ULP		0xE1 /* Temporally hard code */
 #define MXC_CPU_IMX8MQ		0x82
-#define MXC_CPU_IMX8MM		0x83 /* 0x83 is dummy value */
+#define MXC_CPU_IMX8MM		0x85 /* dummy ID */
+#define MXC_CPU_IMX8MML		0x86 /* dummy ID */
+#define MXC_CPU_IMX8MMD		0x87 /* dummy ID */
+#define MXC_CPU_IMX8MMDL	0x88 /* dummy ID */
+#define MXC_CPU_IMX8MMS		0x89 /* dummy ID */
+#define MXC_CPU_IMX8MMSL	0x8a /* dummy ID */
+#define MXC_CPU_IMX8MN		0x8b /* dummy ID */
+#define MXC_CPU_IMX8QXP_A0	0x90 /* dummy ID */
+#define MXC_CPU_IMX8QM		0x91 /* dummy ID */
+#define MXC_CPU_IMX8QXP		0x92 /* dummy ID */
 #define MXC_CPU_VF610		0xF6 /* dummy ID */
 
 #define MXC_SOC_MX6		0x60
@@ -41,6 +51,7 @@
 #define CHIP_REV_1_2            0x12
 #define CHIP_REV_1_5            0x15
 #define CHIP_REV_2_0            0x20
+#define CHIP_REV_2_1            0x21
 #define CHIP_REV_2_5            0x25
 #define CHIP_REV_3_0            0x30
 

arch/arm/include/asm/arch-imx8m/clock.h

@@ -12,7 +12,7 @@
 
 #ifdef CONFIG_IMX8MQ
 #include <asm/arch/clock_imx8mq.h>
-#elif defined(CONFIG_IMX8MM)
+#elif defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
 #include <asm/arch/clock_imx8mm.h>
 #else
 #error "Error no clock.h"