Apparently debug memset (with a 0x55 value) has been overlooked in the
f_thor code.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>

Now it is possible to allocate static request - which receives data from
the host (OUT transaction) to the size of THOR packet.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>

The Samsung's UDC driver is not anymore copying data from USB requests to
aligned internal buffers. Now it works directly in data allocated in the
upper layers like UMS, DFU, THOR.

This change is possible since those gadgets now must take care to allocate
buffers aligned to cache line (CONFIG_SYS_CACHELINE_SIZE).

This can be achieved by using DEFINE_CACHE_ALIGN_BUFFER() or
ALLOC_CACHE_ALIGN_BUFFER() macros. Those take care to allocate buffer
aligned to cache line in both starting address and its size.
Sometimes it is enough to just use memalign() with size being a
multiplication of cache line size.

Test condition
- test HW + measurement: Trats - Exynos4210 rev.1
- test HW Trats2 - Exynos4412 rev.1
400 MiB compressed rootfs image download with `thor 0 mmc 0`

Measurement:
Transmission speed: 27.04 MiB/s

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>

This patch removed obscure restriction on the HW setting of DMA transfers.
Before this change each transaction sent up to 512 bytes (with packet count
equal to 1) for non EP0 transfer.

Now it is possible to setup DMA transaction up to DMA_BUFFER_SIZE.

Test condition
- test HW + measurement: Trats - Exynos4210 rev.1
- test HW Trats2 - Exynos4412 rev.1
400 MiB compressed rootfs image download with `thor 0 mmc 0`

Measurement:
Transmission speed: 20.74 MiB/s

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>

A set of cache operations (both invalidation and flush) were redundant
in the S3C HS OTG Samsung driver:

1. s3c_udc_ep0_zlp - to transmit EP0's ZLP packets one don't need to flush
the cache (since it is the zero length transmission)

2. s3c_udc_pre_setup and s3c_ep0_complete_out - cache invalidation is not
needed when the buffer for OUT EP0 transmission is setup, since no data
has yet arrived.

Cache cleanups presented above don't contribute much to transmission speed
up, hence shall be regarded as cosmetic changes.

3. setdma_rx - here the s3c UDC driver's internal buffers were invalidated.
This call is not needed anymore since we reuse the buffers passed from
gadgets. This is a key contribution to transmission speed improvement.

Test condition
- test HW + measurement: Trats - Exynos4210 rev.1
- test HW Trats2 - Exynos4412 rev.1
400 MiB compressed rootfs image download with `thor 0 mmc 0`

Measurements:

Base values (without improvement):
Transmission speed: 9.51 MiB/s

After the change:
Transmission speed: 10.15 MiB/s

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>

Calls to malloc() have been replaced by memalign. It now provides proper
buffer alignment.

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>

Signed-off-by: Tom Rini <trini@ti.com>

describe a set of default features that distros can rely on being available.
having this common definition means that distros can easily support systems
implementing them.

Signed-off-by: Dennis Gilmore <dennis@ausil.us>

Signed-off-by: Dennis Gilmore <dennis@ausil.us>

People who write (or scripts that auto-generate) extlinux.conf don't
want to know about HW-specific information such as FDT filenames. Create
a new extlinux.conf tag "fdtdir" that specifies only the directory where
FDT files are located, and defer all knowledge of the filename to U-Boot.
The algorithm implemented is:

==========
if $fdt_addr_r is set:
  if "fdt" tag was specified in extlinux.conf:
    load the FDT from the filename in the tag
  else if "fdtdir" tag was specified in extlinux.conf:
    if "fdtfile" is set in the environment:
      load the FDT from filename in "$fdtfile"
    else:
      load the FDT from some automatically generated filename

if no FDT file was loaded, and $fdtaddr is set:
  # This indicates an FDT packaged with firmware
  use the FDT at $fdtaddr
==========

A small part of an example /boot/extlinux.conf might be:

==========
LABEL primary
        LINUX zImage
        FDTDIR ./

LABEL failsafe
        LINUX bkp/zImage
        FDTDIR bkp/
==========

... with /boot/tegra20-seaboard.dtb or /boot/bkp/tegra20-seaboard.dtb
being loaded by the sysboot/pxe code.

Signed-off-by: Stephen Warren <swarren@nvidia.com>

The specification for extlinux.conf[1] states that "fdt" is an alias for
"devicetree". To date, U-Boot only implements "fdt". Rectify that.

[1] http://freedesktop.org/wiki/Specifications/BootLoaderSpec/



Signed-off-by: Stephen Warren <swarren@nvidia.com>

Just to be sure that there is no pending data.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

As tsec and fm drivers checking phydev->link
ensure that u-boot don't try access device if link is not ready.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Add support for U-BOOT SPL. NOR and RAM mode are supported.
There are 3 images in NOR flash. u-boot.img, dtb and kernel.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

It speeds up writing a lot.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Just list one more exception.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

It is nice to see u-boot version.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Command provides just dump subcommand for showing clock
frequencies in a soc.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Stefano Babic <sbabic@denx.de>

IFC registers can be of type Little Endian or big Endian depending upon
Freescale SoC. Here SoC defines the register type of IFC IP.

So update acessor functions with common IFC acessor functions to take care
both type of endianness.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>

The PEXHC PCIe configuration mechanism ensures that the FPGA get
configured at power-up. Since all the PCIe devices should be configured
when the kernel start, u-boot has to take care that the FPGA gets
configured also in other reset scenarios, mostly because of possible
configuration change.

The used mechanism is taken from the km_kirkwood design and adapted to
the kmp204x case (slightly different HW and PCIe configuration).

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Reviewed-by: York Sun <yorksun@freescale.com>

The new prototype and the final series was moved from Micron to Spansion
to have a better reset sequence that is easier to support.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Reviewed-by: York Sun <yorksun@freescale.com>

This define can be used if the ubi boot partition (defined for all
Keymile boards with KM_UBI_PARTITION_NAME_BOOT #define to ubi0) needs
some additionnal boot options.

This is the case for the kmp204x boards since u-boot does not support
NAND Flash subpage accesses on this platform, an additionnal argument
that defines the VID offstet must be given to the kernel.

The UBI cmd line option now looks like this "ubi.mtd=ubi0,2048" on this
platform.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Reviewed-by: York Sun <yorksun@freescale.com>

On the previous HW revision (now unsupported), there was a need for
external DMA signals and thus the I2C3/4 signals were used
DMA1_DONE/ACK/REQ.

These signals now are configured as GPIO[16:19].

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Reviewed-by: York Sun <yorksun@freescale.com>

The kmcoge4 board is the product board derived from the kmlion1
prototype. The main difference between the 2 boards is that the kmcoge4
does not configure the Local Bus controller for LCS2.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
[York Sun: Minor change to boards.cfg to keep targets in order]
Signed-off-by: York Sun <yorksun@freescale.com>

According to the errata, some bits of an undocumented register in the
DCSR must be set for every core in order to avoid a possible data or
instruction corruption.

This is required for the 2.0 revision of the P2041 that should be used
as soon as available in our design.

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Reviewed-by: York Sun <yorksun@freescale.com>

This patch adds support for using some GPIOs that are connected to the
I2C bus to force the bus lines state and perform some bus deblocking
sequences.

The KM common deblocking algorithm from board/keymile/common/common.c is
used. The GPIO lines used for deblocking the I2C bus are some external
GPIOs provided by the QRIO CPLD:
  - SCL = GPIOA_20
  - SDA = GPIOA_21

The QRIO GPIOs act in an open-drain-like manner, for 0 the line is
driven low and for 1 the GPIO is set as input and the line gets
pulled-up.

Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Reviewed-by: York Sun <yorksun@freescale.com>

The QRIO GPIO functions can be of general interest. They are thus added
to a qrio.c and their prototype are available from kmp204x.h. The QRIO
prst function are also included in this file, as well as the functions
required for the I2C deblocking support (open-drain).

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
[York Sun: Remove extra blank line in board/keymile/kmp204x/qrio.c]
Signed-off-by: York Sun <yorksun@freescale.com>

Make use of the QRIO1 32bit register at 0x20 as bootcounter register
Check for BOOTCOUNT_MAGIC pattern when before bootcounter value is read

Signed-off-by: Rainer Boschung <rainer.boschung@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
[York Sun: Minor change to commit message]
Signed-off-by: York Sun <yorksun@freescale.com>

This covers only non-L2 switch ethernet interfaces i.e.
RGMII and SGMII interface for both T1040RDB and T1042RDB_PI

T1040RDB is configured as serdes protocol 0x66 which can
support following interfaces
    2 RGMIIS on DTSEC4, DTSEC5
    1 SGMII on DTSEC3

T1042RDB_PI is configured as serdes protocol 0x06 which can
support following interfaces
    2 RGMIIS on DTSEC4, DTSEC5

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
[York Sun: Minor change in commit message]
Signed-off-by: York Sun <yorksun@freescale.com>

Define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE macro for enabling dual
phy in t1040

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

Add usb2 node entry to hwconfig default

Remove DDR controller interleaving from hwconfig

Move SPI related macros out of "#ifdef CONFIG_SPIFLASH"

Add CONFIG_SYS_CSPR2_EXT to make CPLD accessible in u-boot

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Fix commit message]
Signed-off-by: York Sun <yorksun@freescale.com>

Add usb2 node entry in "hwconfig string"

Remove controller interleaving from hwconfig string as T1040
has only one DDR conroller

SPI related macros which were earlier under #ifdef CONFIG_SPIFLASH
are move outside so that they are defined for all cases as these
macros are also used by other u-boot code

Add CONFIG_SYS_CSPR2_EXT to make CPLD accessible

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
[York Sun: Minor change to commit message]
Signed-off-by: York Sun <yorksun@freescale.com>

Enable entherent for T1040QDS. It enables FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5
    Define MDIO related configs
    Added eth.c file
    Update t1040.c to support RGMII and SGMII
    Update t1040qds.c to support ethernet
    Define the PHY address

Signed-off-by: Arpit Goel <B44344@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: remove dash from commit message]
Signed-off-by: York Sun <yorksun@freescale.com>

T1040 has only one SerDes block. so update the code accordingly.

Also, add support of SerDes Protocol 0x00, 0x06, 0x40, 0x69 0x85,
0xA7 and 0xAA

Signed-off-by: Arpit Goel <B44344@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

Due to increased size of u-boot, FMAN ucode start address has been shifted
by 256KB causing a overlap with rootfs start address.

Update rootfs start address to reflect correct memory map.

Also fix minor typo in README

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>