- May 18, 2016
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Alex Porosanu authored
For SoCs that contain multiple SEC engines, each of them needs to be initialized (by means of initializing among others the random number generator). Signed-off-by:
Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Alex Porosanu authored
Some SOCs, specifically the ones in the C29x familiy can have multiple security engines. This patch adds a system configuration define which indicates the maximum number of SEC engines that can be found on a SoC. Signed-off-by:
Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Alex Porosanu authored
Freescale PPC SoCs do not hard-code security engine's Job Ring 0 address, rather a define is used. This patch adds the same functionality to the ARM based SoCs (i.e. LS1/LS2 and i.MX parts) Signed-off-by:
Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Qianyu Gong authored
MMCSD_MODE_FAT has been renamed to MMCSD_MODE_FS by commit 205b4f33. Signed-off-by:
Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Qianyu Gong authored
MMCSD_MODE_FAT has be renmaed to MMCSD_MODE_FS by commit 205b4f33. Signed-off-by:
Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Qianyu Gong authored
init_early_memctl_regs() is also be called in board_early_init_f(). So remove the duplicated call in spl code. Signed-off-by:
Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Qianyu Gong authored
Using u16 for cfg_rcw_src and u8 for sd1refclk_sel is enough. Signed-off-by:
Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Qianyu Gong authored
gd->env_addr will be initialized in env_init() in common/env_nowhere.c if CONFIG_ENV_IS_NOWHERE is defined. So no need to do it again. Signed-off-by:
Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Qianyu Gong authored
IFC won't be initialized in U-Boot if QSPI is enabled on LS1043AQDS. So this patch could fix 'sync abort' caused by autoboot that tries to access IFC address. Signed-off-by:
Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Qianyu Gong authored
The current 'cpld reset' will just write global_rst register but couldn't switch to NOR boot if the board's switches are for NAND/SD boot. So need to write rcw source registers for NOR boot as well. Signed-off-by:
Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Vincent Siles authored
Mix usage of uint32_t and u32 fixed in favor of u32. Signed-off-by:
Vincent Siles <vincent.siles@provenrun.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Vincent Siles authored
On the LS102x boards, in order to initialize the ICID values of masters, the dev_stream_id array holds absolute offsets from the base of SCFG. In ls102xa_config_ssmu_stream_id, the base pointer is cast to uint32_t * before adding the offset, leading to an invalid address. Casting it to void * solves the issue. Signed-off-by:
Vincent Siles <vincent.siles@provenrun.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Alison Wang authored
As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b06, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by:
Alison Wang <alison.wang@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Prabhakar Kushwaha authored
As per new PHY framework, DPNI naming convetion is no more used. Use new naming convention. Signed-off-by:
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Aneesh Bansal authored
Define CONFIG_FSL_CAAM for LS2080 which would enable call to sec_init() during U-Boot. Signed-off-by:
Aneesh Bansal <aneesh.bansal@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Yuan Yao authored
The address value and size value set for QSPI dts node "reg" property have type of u64 on arm64. Signed-off-by:
Yuan Yao <yao.yuan@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Yuan Yao authored
The S25FS-S family physical sectors may be configured as a hybrid combination of eight 4-kB parameter sectors at the top or bottom of the address space with all but one of the remaining sectors being uniform size. The default status of the flash is in this hybrid architecture. The parameter sectors and the uniform sectors have different erase commands. This patch disable the hybrid sector architecture then the flash will has uniform sector size and uniform erase command. This configuration is temporary, the flash will revert to hybrid architecture after power on reset. Signed-off-by:
Yuan Yao <yao.yuan@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Yuan Yao authored
The flash type of LS2085AQDS QSPI is S25FS256S. It has special write any device register command and read any device register command. This patch enable support for those commands. Signed-off-by:
Yuan Yao <yao.yuan@nxp.com> Signed-off-by:
Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Yuan Yao authored
QSPI controller automatic enable the chipselect signal according the dest AMBA memory address. Now we distribute the AMBA memory zone averagely to every chipselect slave device according chipselect numbers got from dts node. Signed-off-by:
Yuan Yao <yao.yuan@nxp.com> Signed-off-by:
Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Yuan Yao authored
The address value and size value get from dts "reg" property have type of u64 on arm64. If we assign those values to "u32" variables, driver can't work correctly. Converting the type of those variables to fdt_xxx_t. Signed-off-by:
Yuan Yao <yao.yuan@nxp.com> Signed-off-by:
Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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- May 17, 2016
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Alex Porosanu authored
For Qoriq PPC&ARM v7 platforms, the crypto node is being fixup'ed in order to update the SEC internal version (aka SEC ERA). This patch adds the same functionality to the ARMv8 SoCs. Signed-off-by:
Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Prabhakar Kushwaha authored
Update MAINTAINERS file for ls2080aqds and ls2080ardb platforms. Signed-off-by:
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Shengzhou Liu authored
Optimize DDR timing for good margins to support new Transcend and Apacer DDR4 UDIMM besides current Micron UDIMM. Verified 1333MT/s, 1600MT/s, 1866MT/s, 2133MT/s rate with following UDIMM on LS2080ARDB. - Micron UDIMM: MTA18ASF1G72AZ-2G1A1Z - Apacer UDIMM: 78.C1GM4.AF10B - Transcend UDIMM: TS1GLH72V1H Signed-off-by:
Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Shengzhou Liu authored
The initial training for the DDRC may provide results that are not optimized. The workaround provides better read timing margins. Signed-off-by:
Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Shengzhou Liu authored
Per the latest erratum document, update step 4 and step 8, only DEBUG_29[21] is changed, all other bits should not be changed. Signed-off-by:
Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Shengzhou Liu authored
Barrier transactions from CCI400 need to be disabled till the DDR is configured, otherwise it may lead to system hang. The patch adds workaround to fix the erratum. Signed-off-by:
Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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- May 16, 2016
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Tom Rini authored
Signed-off-by:
Tom Rini <trini@konsulko.com>
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- May 15, 2016
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Hans de Goede authored
Reported-and-tested-by:
Dennis Gilmore <dennis@ausil.us> Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Acked-by:
Ian Campbell <ijc@hellion.org.uk>
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- May 13, 2016
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Heiko Schocher authored
update tbot documentation in U-Boot, as I just merged the event system into tbots master branch. Signed-off-by:
Heiko Schocher <hs@denx.de>
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Heiko Schocher authored
test/py raises an error, if a board has not enabled bdi command > pytest.skip('bdinfo command not supported') E NameError: global name 'pytest' is not defined import pytest in test/py/u_boot_utils.py fixes this. Signed-off-by:
Heiko Schocher <hs@denx.de> Reviewed-by:
Stephen Warren <swarren@nvidia.com>
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- May 12, 2016
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Andre Przywara authored
Commit bfb33f0b ("sunxi: mctl_mem_matches: Add missing memory barrier") broke compilation for the Pine64, as dram_helper.c now includes <asm/armv7.h>, which does not compile on arm64. Fix this by moving all barrier instructions into a separate header file, which can easily be shared between arm and arm64. Also extend the inline assembly to take the "sy" argument, which is optional for ARMv7, but mandatory for v8. This fixes compilation for 64-bit sunxi boards (Pine64). Acked-by:
Ian Campbell <ijc@hellion.org.uk> Signed-off-by:
Andre Przywara <andre.przywara@arm.com>
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- May 10, 2016
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Dinh Nguyen authored
Update the pinmux and pll configuration for the Cyclone5 RevE or later devkit. Signed-off-by:
Dinh Nguyen <dinguyen@opensource.altera.com>
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Fabio Estevam authored
CONFIG_OF_LIBFDT needs to be selected to avoid the following boot problem: reading zImage 6346216 bytes read in 118 ms (51.3 MiB/s) Booting from mmc ... reading imx7d-warp.dtb 32593 bytes read in 11 ms (2.8 MiB/s) Kernel image @ 0x80800000 [ 0x000000 - 0x60d5e8 ] FDT and ATAGS support not compiled in - hanging ### ERROR ### Please RESET the board ### Signed-off-by:
Fabio Estevam <fabio.estevam@nxp.com>
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- May 07, 2016
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git://git.denx.de/u-boot-socfpgaTom Rini authored
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git://git.denx.de/u-boot-usbTom Rini authored
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- May 06, 2016
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Peng Fan authored
Reported by Coverity: Logically dead code (DEADCODE) dead_error_line: Execution cannot reach this statement: (f_dfu->strings + --i).s = .... If calloc failed, i is still 0 and no need to call free, so discard the dead code. Signed-off-by:
Peng Fan <van.freenix@gmail.com> Cc: "Łukasz Majewski" <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de>
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Peng Fan authored
When dfu_fill_entity fail, need to free dfu to avoid memory leak. Reported by Coverity: " Resource leak (RESOURCE_LEAK) leaked_storage: Variable dfu going out of scope leaks the storage it points to. " Signed-off-by:
Peng Fan <van.freenix@gmail.com> Cc: "Łukasz Majewski" <l.majewski@samsung.com> Cc: Marek Vasut <marex@denx.de>
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Stefan Roese authored
With patch c998da0d (usb: Change power-on / scanning timeout handling), the USB scanning is started earlier and with a smaller timeout. This resulted on SoCFPGA (using the DWC2 driver) in some USB sticks not getting detected any more. This patch now adds a 1 second delay (in the host mode only) to the DWC2 driver before the scanning is started. With this delay, now all problematic USB keys are detected successfully again. And there is no need any more to change the delay / timeout in the common USB code (usb_hub.c). Signed-off-by:
Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Marek Vasut <marex@denx.de>
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Marek Vasut authored
The code shouldn't continue probing the port if get_port_status() failed. Signed-off-by:
Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Stefan Roese <sr@denx.de> Cc: Stephen Warren <swarren@nvidia.com>
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Marek Vasut authored
The Kingston DT Ultimate USB 3.0 stick is sensitive to this first Get Descriptor request and if the request is not in a separate microframe, the stick refuses to operate. Add slight delay, which is enough for one microframe to pass on any USB spec revision. Signed-off-by:
Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Stefan Roese <sr@denx.de> Cc: Stephen Warren <swarren@nvidia.com>
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