- Oct 18, 2016
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Masahiro Yamada authored
- Rephrase the toolchains section. Leave only Linaro toolchains since it is the most tested these days. - Add build instruction for ARMv8 SoC boards - Add information about "ddrmphy" command Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com>
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Masahiro Yamada authored
Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com>
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- Oct 12, 2016
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Bin Meng authored
This converts coreboot to use DM framebuffer driver. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> Reviewed-by:
Simon Glass <sjg@chromium.org>
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Bin Meng authored
The kernel load address for zboot should be 0x1000000. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> Reviewed-by:
Simon Glass <sjg@chromium.org>
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Bin Meng authored
For some unknown reason, coreboot framebuffer driver never works on QEMU since day 1. It seems the driver only works on real hardware. Document this issue. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> Reviewed-by:
Simon Glass <sjg@chromium.org>
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- Oct 07, 2016
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Stefan Agner authored
Add device model enabled PMIC driver for Ricoh RN5T567 PMIC used on Colibri iMX7. Signed-off-by:
Stefan Agner <stefan.agner@toradex.com> Reviewed-by:
Simon Glass <sjg@chromium.org>
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Stefan Agner authored
Support instatiation through device tree. Also parse the fsl,dte-mode property to determine whether DTE mode shall be used. Signed-off-by:
Stefan Agner <stefan.agner@toradex.com> Reviewed-by:
Simon Glass <sjg@chromium.org>
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Jelle van der Waa authored
Signed-off-by:
Jelle van der Waa <jelle@vdwaa.nl>
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Simon Glass authored
This should be CONFIG_SYS_MAX_NAND_DEVICE. Fix it. Signed-off-by:
Simon Glass <sjg@chromium.org> Acked-by:
Scott Wood <oss@buserror.net> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Simon Glass authored
This option is not used now. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Simon Glass authored
The only content of this file is CONFIG options which are no-longer present in U-Boot. Drop it. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Simon Glass authored
This issue covered by this doc appears to be fixed, so let's remove the README. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com> Reviewed-by:
York Sun <york.sun@nxp.com> Acked-by:
Andreas Bießmann <andreas@biessmann.org>
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Simon Glass authored
There appear to be neither implemented nor used. Drop them. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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- Oct 04, 2016
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Fabio Estevam authored
Correct name is "Boundary Devices". Signed-off-by:
Fabio Estevam <fabio.estevam@nxp.com>
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- Oct 02, 2016
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Andrew F. Davis authored
Add a section describing the additional boot types used on AM33xx secure devices. Signed-off-by:
Andrew F. Davis <afd@ti.com> Reviewed-by:
Tom Rini <trini@konsulko.com> Acked-by:
Lokesh Vutla <lokeshvutla@ti.com>
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Petr Kulhavy authored
In both DOS and ISO partition tables the same code to create partition name like "hda1" was repeated. Code moved to into a new function part_set_generic_name() in part.c and optimized. Added recognition of MMC and SD types, name is like "mmcsda1". Signed-off-by:
Petr Kulhavy <brain@jikos.cz> Reviewed-by:
Tom Rini <trini@konsulko.com> Acked-by:
Steve Rae <steve.rae@raedomain.com> Reviewed-by:
Simon Glass <sjg@chromium.org>
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Petr Kulhavy authored
Add special target "mbr" (otherwise configurable via CONFIG_FASTBOOT_MBR_NAME) to write MBR partition table. Partitions are now searched using the generic function which finds any partiiton by name. For MBR the partition names hda1, sda1, etc. are used. Signed-off-by:
Petr Kulhavy <brain@jikos.cz> Reviewed-by:
Tom Rini <trini@konsulko.com> Acked-by:
Steve Rae <steve.rae@raedomain.com> Reviewed-by:
Simon Glass <sjg@chromium.org>
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- Sep 21, 2016
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Paul Burton authored
This patch introduces support for building U-Boot to run on the MIPS Boston development board. This is a board built around an FPGA & an Intel EG20T Platform Controller Hub, used largely as part of the development of new CPUs and their software support. It is essentially the successor to the older MIPS Malta board. Signed-off-by:
Paul Burton <paul.burton@imgtec.com>
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- Sep 07, 2016
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Wenbin Song authored
Use environment variable "kernel_addr_r" to indicate the location in RAM where FIT image will be stored. Use label command "kernel" to indicate which <path> the FIT image at. Signed-off-by:
Wenbin Song <wenbin.song@nxp.com>
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- Sep 06, 2016
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John Keeping authored
When enabling a fixed regulator, it may take some time to rise to the correct voltage. If we do not delay here then subsequent operations will fail. Signed-off-by:
John Keeping <john@metanate.com> Reviewed-by:
Tom Rini <trini@konsulko.com> Reviewed-by:
Simon Glass <sjg@chromium.org>
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- Aug 26, 2016
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Masahiro Yamada authored
Most of them are my mistakes. Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com>
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- Aug 16, 2016
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Simon Glass authored
This feature is not supported. Document this, and add some details on how it might be implemented. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
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Simon Glass authored
UEFI is commonly used on x86. Add a reference to U-Boot's support for this in the x86 README. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
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Simon Glass authored
The README indicates that this is not supported, but this is no-longer true. Update the text to indicate this and describe the FIT changes required. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
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Stefan Roese authored
The debug FSP image is bigger in size than the normal FSP image. This patch adds a small description on how to use this FSP debug version by changing CONFIG_FSP_ADDR. Signed-off-by:
Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
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- Aug 15, 2016
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Chris Zankel authored
The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core provided by Cadence. This is the first part of the basic architecture port with changes to common files. The 'arch/xtensa' directory, and boards and additional drivers will be in separate commits. Signed-off-by:
Chris Zankel <chris@zankel.net> Signed-off-by:
Max Filippov <jcmvbkbc@gmail.com> Reviewed-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Tom Rini <trini@konsulko.com>
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Wenyou Yang authored
Bring in required device tree file and bindings from Linux. Signed-off-by:
Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by:
Andreas Bießmann <andreas@biessmann.org> Reviewed-by:
Simon Glass <sjg@chromium.org>
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Songjun Wu authored
DT binding documentation for atmel i2c driver. Signed-off-by:
Songjun Wu <songjun.wu@atmel.com> Reviewed-by:
Heiko Schocher <hs@denx.de> Acked-by:
Heiko Schocher <hs@denx.de>
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- Aug 08, 2016
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Vignesh R authored
TI's PCF8575 is a 16-bit I2C GPIO expander.The device features a 16-bit quasi-bidirectional I/O ports. Each quasi-bidirectional I/O can be used as an input or output without the use of a data-direction control signal. The I/Os should be high before being used as inputs. Read the device documentation for more details[1]. This driver is based on pcf857x driver available in Linux v4.7 kernel. It supports basic reading and writing of gpio pins. [1] http://www.ti.com/lit/ds/symlink/pcf8575.pdf Signed-off-by:
Vignesh R <vigneshr@ti.com> Reviewed-by:
Tom Rini <trini@konsulko.com> Reviewed-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Mugunthan V N <mugunthanvnm@ti.com>
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- Aug 05, 2016
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Xu Ziyuan authored
Miniarm is a rockchip rk3288 based development board, which has lots of interface such as HDMI, USB, micro-SD card, Audio etc. Signed-off-by:
Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by:
Simon Glass <sjg@chromium.org>
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- Aug 04, 2016
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Stephen Warren authored
In Tegra186, the BPMP (Boot and Power Management Processor) owns certain HW devices, such as the I2C controller for the power management I2C bus. Software running on other CPUs must perform IPC to the BPMP in order to execute transactions on that I2C bus. This binding describes an I2C bus that is accessed in such a fashion. Signed-off-by:
Stephen Warren <swarren@nvidia.com> Reviewed-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Stephen Warren authored
The BPMP implements some services which must be represented by separate nodes. For example, it can provide access to certain I2C controllers, and the I2C bindings represent each I2C controller as a device tree node. Update the binding to describe how the BPMP supports this. Signed-off-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Stephen Warren authored
The Tegra BPMP (Boot and Power Management Processor) is a separate auxiliary CPU embedded into Tegra to perform power management work, and controls related features such as clocks, resets, power domains, PMIC I2C bus, etc. These bindings dictate how to represent the BPMP in device tree. Signed-off-by:
Stephen Warren <swarren@nvidia.com> Reviewed-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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Stephen Warren authored
The DT binding for the Tegra186 HSP module apparently wasn't quite final when I posted initial U-Boot support for it. Add the final DT binding doc and adapt all code and DT files to match it. Signed-off-by:
Stephen Warren <swarren@nvidia.com> Reviewed-by:
Simon Glass <sjg@chromium.org> Signed-off-by:
Tom Warren <twarren@nvidia.com>
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- Aug 02, 2016
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Jaehoon Chung authored
Update the mmc maintainer from Pantelis to me. Acked-by:
Pantelis Antoniou <pantelis.antoniou@konsulko.com> Signed-off-by:
Jaehoon Chung <jh80.chung@samsung.com>
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- Aug 01, 2016
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Simon Glass authored
It is confusing to mention MAKEALL when it is not the normal way of building U-Boot anymore. Update the documentation to suit. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Tom Rini <trini@konsulko.com>
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- Jul 31, 2016
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jk.kernel@gmail.com authored
PopMetal is a rockchip rk3288 based board made by ChipSpark, which has many interface such as HDMI, VGA, USB, micro-SD card, WiFi, Audio and Gigabit Ethernet. Signed-off-by:
Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by:
Simon Glass <sjg@chromium.org>
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jk.kernel@gmail.com authored
Fennec is a RK3288-based development board with 2 USB ports, HDMI, micro-SD card, audio and WiFi and Gigabit Ethernet. It also includes on-board 8GB eMMC and 2GB of SDRAM. Expansion connectors provides access to display pins, I2C, SPI, UART and GPIOs. Signed-off-by:
Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by:
Simon Glass <sjg@chromium.org>
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- Jul 26, 2016
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Xu Ziyuan authored
Introduce how to use fastboot feature on rk3288. Signed-off-by:
Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by:
Simon Glass <sjg@chromium.org>
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Xu Ziyuan authored
evb-3288 board RK3288-based development board with 2 USB ports, HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet. It also includes on-board 8G eMMC and 2GB of SDRAM. Expansion connector provide access to display pins, I2C, SPI, UART and GPIOs. This add some basic files required to allow the board to output serial messaged and can run command(mmc info etc). evb-rk3288 also supports booting from eMMC or SD card, the default is eMMC. Signed-off-by:
Ziyuan Xu <xzy.xu@rock-chips.com> Reviewed-by:
Simon Glass <sjg@chromium.org>
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