Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

Enable single-bit error counter when memory was cleared by ddr controller.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

Some device trees have a mac-address property, some have local-mac-address,
and some have both.  To support all of these device trees, ftp_cpu_setup()
should write the MAC address to mac-address and local-mac-address, if they
exist.

Signed-off-by: Timur Tabi <timur@freescale.com>

* Cleaned up the TSR[WIS] clearing
* Cleaned up DMA initialization

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>

Recognize new SVR values, and add a few register definitions

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>

Add board port under new board/freescale directory
structure and reuse existing PIXIS FPGA support there.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>

The PCI I/O space mapping for Freescale MPC8540ADS board was broken by commit
52c7a68b which failed to update the #define's
describing the local address window used for the PCI I/O space accesses -- fix
this and carry over the necessary changes into the MPC8560ADS code since the
PCI I/O space mapping was also broken for this board (by the earlier commit
08745460).  Add the comments clarifying how
the PCI I/O space must be mapped to all the MPC85xx board config. headers.

Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>

 board/mpc8540ads/init.S      |    4 ++--
 board/mpc8560ads/init.S      |    4 ++--
 include/configs/MPC8540ADS.h |    5 ++---
 include/configs/MPC8541CDS.h |    2 +-
 include/configs/MPC8548CDS.h |    2 +-
 include/configs/MPC8560ADS.h |    8 ++++----
 6 files changed, 12 insertions(+), 13 deletions(-)

The following patch fixes the e500 v2 core reset bug.
For e500 v2 core, a new reset control register is added to reset the
processor.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>

Remove the fixed TLB and LAW entry nubmer. Use actually TLB and LAW
entry number to control the loop.  This can reduce the potential risk
for the 85xx processor increasing its TLB adn LAW entry number.

Signed-off-by: Swarthout Edward <swarthout@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>

Fix the 85xxcds tsec bug.
When enable PCI, tsec.o should be added to u-boot.lds to make tsec work.

Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>

This patch apply workaround of CPU2 errata on MPC8548CDS board.

Signed-off-by: Ebony Zhu <ebony.zhu@freescale.com>

This patch disables MPC8548CDS 2T_TIMING for DDR by default.

Signed-off-by: Ebony Zhu <ebony.zhu@freescale.com>

Enable PCI function and add PEX & rapidio memory map on MPC8548CDS
board.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>

Signed-off-by: Wolfgang Denk <wd@denx.de>

Signed-off-by: Detlev Zundel <dzu@denx.de>

G2 core reference manual says decrementer and time base
are decreasing/increasing once every 4 bus clock cycles.
Lets fix it, so time in Linux won't run twice as fast

Signed-off-by: Domen Puncer <domen.puncer@telargo.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>

What was suppose to be a stack variable was declared as a pointer,
  overwriting random memory.
Also moved the libfdt.a requirement into the main Makefile.  That is
  The U-Boot Way.

Signed-off-by: Wolfgang Denk <wd@denx.de>

Signed-off-by: Wolfgang Denk <wd@denx.de>

Sigend-off-by: Wolfgang Denk <wd@denx.de>

Signed-off-by: Wolfgang Denk <wd@denx.de>

Signed-off-by: Domen Puncer <domen.puncer@telargo.com>

Signed-off-by: Stefan Roese <sr@denx.de>

Now 405EZ ports also show upon bootup from which boot device
they are configured to boot:

U-Boot 1.2.0-gd3832e8f-dirty (Apr 18 2007 - 07:47:05)

CPU:   AMCC PowerPC 405EZ Rev. A at 199.999 MHz (PLB=133, OPB=66, EBC=66 MHz)
       Bootstrap Option E - Boot ROM Location EBC (32 bits)
       16 kB I-Cache 16 kB D-Cache
Board: Acadia - AMCC PPC405EZ Evaluation Board

Signed-off-by: Stefan Roese <sr@denx.de>

Add Konstantin Kletschke for scb9328.
Signed-off-by: Peter Pearse <peter.pearse@arm.com>

U-Boot part of Lite5200b low power mode support.
Puts SDRAM out of self-refresh and transfers control to
address saved at physical 0x0.

Signed-off-by: Domen Puncer <domen.puncer@telargo.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>