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Commit f2a8279e authored by Suman Anna's avatar Suman Anna Committed by Tom Rini
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ARM: keystone2: K2G: power-off DSP during boot


The DSPs are powered on by default upon a Power ON reset, and
they are powered off on current Keystone 2 SoCs - K2HK, K2L, K2E
during the boot in u-boot. This is not functional on K2G though.
Extend the existing DSP power-off support to the only DSP present
on K2G. Do note that the PSC clock domain module id for DSP on K2G
differs from that of previous Keystone2 SoCs.

Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
Signed-off-by: default avatarNishanth Menon <nm@ti.com>
Reviewed-by: default avatarTom Rini <trini@konsulko.com>
parent 4ed8b2c9
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...@@ -10,7 +10,7 @@ ...@@ -10,7 +10,7 @@
#ifndef __ASM_ARCH_HARDWARE_K2G_H #ifndef __ASM_ARCH_HARDWARE_K2G_H
#define __ASM_ARCH_HARDWARE_K2G_H #define __ASM_ARCH_HARDWARE_K2G_H
#define KS2_NUM_DSPS 0 #define KS2_NUM_DSPS 1
/* Power and Sleep Controller (PSC) Domains */ /* Power and Sleep Controller (PSC) Domains */
#define KS2_LPSC_ALWAYSON 0 #define KS2_LPSC_ALWAYSON 0
...@@ -30,7 +30,10 @@ ...@@ -30,7 +30,10 @@
#define KS2_LPSC_MCASP 15 #define KS2_LPSC_MCASP 15
#define KS2_LPSC_SR 16 #define KS2_LPSC_SR 16
#define KS2_LPSC_MSMC 17 #define KS2_LPSC_MSMC 17
#define KS2_LPSC_GEM 18 #ifdef KS2_LPSC_GEM_0
#undef KS2_LPSC_GEM_0
#endif
#define KS2_LPSC_GEM_0 18
#define KS2_LPSC_ARM 19 #define KS2_LPSC_ARM 19
#define KS2_LPSC_ASRC 20 #define KS2_LPSC_ASRC 20
#define KS2_LPSC_ICSS 21 #define KS2_LPSC_ICSS 21
......
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