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Commit ef4cf5ae authored by David Wu's avatar David Wu Committed by Philipp Tomsich
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rockchip: clk: Add SARADC clock support for rk3288 


The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.

Signed-off-by: default avatarDavid Wu <david.wu@rock-chips.com>
Reviewed-by: default avatarPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: default avatarPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
parent 2e4ce50d
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