add AcTux-2 board support

Signed-off-by: Michael Schwingen <michael@schwingen.org>

board/actux2/Makefile

+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= actux2.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/actux2/actux2.c

+/*
+ * (C) Copyright 2007
+ * Michael Schwingen, michael@schwingen.org
+ *
+ * (C) Copyright 2006
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2002
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <asm/arch/ixp425.h>
+#include <asm/io.h>
+
+#include <miiphy.h>
+
+#include "actux2_hw.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init (void)
+{
+	gd->bd->bi_arch_number = MACH_TYPE_ACTUX2;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = 0x00000100;
+
+	GPIO_OUTPUT_ENABLE (CFG_GPIO_IORST);
+	GPIO_OUTPUT_ENABLE (CFG_GPIO_ETHRST);
+	GPIO_OUTPUT_ENABLE (CFG_GPIO_DSR);
+	GPIO_OUTPUT_ENABLE (CFG_GPIO_DCD);
+
+	GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST);
+	GPIO_OUTPUT_CLEAR (CFG_GPIO_ETHRST);
+
+	GPIO_OUTPUT_CLEAR (CFG_GPIO_DSR);
+	GPIO_OUTPUT_SET (CFG_GPIO_DCD);
+
+	/* Setup GPIO's for Interrupt inputs */
+	GPIO_OUTPUT_DISABLE (CFG_GPIO_DBGINT);
+	GPIO_OUTPUT_DISABLE (CFG_GPIO_ETHINT);
+
+	/* Setup GPIO's for 33MHz clock output */
+	GPIO_OUTPUT_ENABLE (CFG_GPIO_PCI_CLK);
+	GPIO_OUTPUT_ENABLE (CFG_GPIO_EXTBUS_CLK);
+	*IXP425_GPIO_GPCLKR = 0x011001FF;
+
+	/* CS1: IPAC-X */
+	*IXP425_EXP_CS1 = 0x94d10013;
+	/* CS5: Debug port */
+	*IXP425_EXP_CS5 = 0x9d520003;
+	/* CS6: HW release register */
+	*IXP425_EXP_CS6 = 0x81860001;
+	/* CS7: LEDs */
+	*IXP425_EXP_CS7 = 0x80900003;
+
+	udelay (533);
+	GPIO_OUTPUT_SET (CFG_GPIO_IORST);
+	GPIO_OUTPUT_SET (CFG_GPIO_ETHRST);
+
+	ACTUX2_LED1 (1);
+	ACTUX2_LED2 (0);
+	ACTUX2_LED3 (0);
+	ACTUX2_LED4 (0);
+
+	return 0;
+}
+
+/*
+ * Check Board Identity
+ */
+int checkboard (void)
+{
+	char revision;
+	char *s = getenv ("serial#");
+
+	puts ("Board: AcTux-2 rev.");
+	putc (ACTUX2_BOARDREL + 'A' - 1);
+	putc ('\n');
+
+	return (0);
+}
+
+int dram_init (void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return (0);
+}
+
+/*************************************************************************
+ * get_board_rev() - setup to pass kernel board revision information
+ * 0 = reserved
+ * 1 = Rev. A
+ * 2 = Rev. B
+ *************************************************************************/
+u32 get_board_rev (void)
+{
+	return ACTUX2_BOARDREL;
+}
+
+void reset_phy (void)
+{
+	int i;
+
+	/* init IcPlus IP175C ethernet switch to native IP175C mode */
+	miiphy_write ("NPE0", 29, 31, 0x175C);
+}

board/actux2/actux2_hw.h

+/*
+ * (C) Copyright 2007
+ * Michael Schwingen, michael@schwingen.org
+ *
+ * hardware register definitions for the AcTux-2 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ACTUX2_HW_H
+#define _ACTUX2_HW_H
+
+/* 0 = LED off,1 = green, 2 = red, 3 = orange */
+#define ACTUX2_LED1(a)	writeb((a ? 2 : 0), IXP425_EXP_BUS_CS7_BASE_PHYS + 0)
+#define ACTUX2_LED2(a)	writeb((a ? 2 : 0), IXP425_EXP_BUS_CS7_BASE_PHYS + 1)
+#define ACTUX2_LED3(a)	writeb((a ? 0 : 2), IXP425_EXP_BUS_CS7_BASE_PHYS + 2)
+#define ACTUX2_LED4(a)	writeb((a ? 0 : 2), IXP425_EXP_BUS_CS7_BASE_PHYS + 3)
+
+#define ACTUX2_DBG_PORT	IXP425_EXP_BUS_CS5_BASE_PHYS
+#define ACTUX2_BOARDREL	(readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F)
+#define ACTUX2_OPTION	(readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0xF0)
+
+/*
+ * GPIO settings
+ */
+#define CFG_GPIO_DBGINT			0
+#define CFG_GPIO_ETHINT			1
+#define CFG_GPIO_ETHRST			2	/* Out */
+#define CFG_GPIO_LED5_GN		3	/* Out */
+#define CFG_GPIO_UNUSED4		4
+#define CFG_GPIO_UNUSED5		5
+#define CFG_GPIO_DSR			6	/* Out */
+#define CFG_GPIO_DCD			7	/* Out */
+#define CFG_GPIO_IPAC_INT		8
+#define CFG_GPIO_DBGJUMPER		9
+#define CFG_GPIO_BUTTON1		10
+#define CFG_GPIO_DBGSENSE		11
+#define CFG_GPIO_DTR			12
+#define CFG_GPIO_IORST			13	/* Out */
+#define CFG_GPIO_PCI_CLK		14	/* Out */
+#define CFG_GPIO_EXTBUS_CLK		15	/* Out */
+
+#endif

board/actux2/config.mk

+TEXT_BASE = 0x00e00000
+
+# include NPE ethernet driver
+BOARDLIBS = cpu/ixp/npe/libnpe.a

board/actux2/u-boot.lds

+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
+OUTPUT_ARCH (arm)
+ENTRY (_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN (4);
+	.text : {
+		cpu/ixp/start.o(.text)
+		lib_generic/string.o(.text)
+		lib_generic/vsprintf.o(.text)
+		lib_arm/board.o(.text)
+		common/dlmalloc.o(.text)
+		cpu/ixp/cpu.o(.text)
+
+		. = env_offset;
+		common/environment.o (.ppcenv)
+
+		* (.text)
+	}
+
+	. = ALIGN (4);
+	.rodata : {
+		*(.rodata)
+	}
+
+	. = ALIGN (4);
+	.data : {
+		*(.data)
+	}
+
+	. = ALIGN (4);
+	.got : {
+		*(.got)
+	}
+
+	. =.;
+	__u_boot_cmd_start =.;
+	.u_boot_cmd : {
+		*(.u_boot_cmd)
+	}
+	__u_boot_cmd_end =.;
+
+	. = ALIGN (4);
+	__bss_start =.;
+	.bss (NOLOAD): {
+		*(.bss)
+	}
+	_end =.;
+}

include/configs/actux2.h

+/*
+ * (C) Copyright 2007
+ * Michael Schwingen, michael@schwingen.org
+ *
+ * Configuration settings for the AcTux-2 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_IXP425			1
+#define CONFIG_ACTUX2			1
+
+#define CONFIG_DISPLAY_CPUINFO		1
+#define CONFIG_DISPLAY_BOARDINFO	1
+
+#define CFG_IXP425_CONSOLE		IXP425_UART2
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_BOOTDELAY		5
+#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
+
+/***************************************************************
+ * U-boot generic defines start here.
+ ***************************************************************/
+#undef CONFIG_USE_IRQ
+
+/* Size of malloc() pool */
+#define CFG_MALLOC_LEN			(CFG_ENV_SIZE + 128*1024)
+/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_SIZE		128
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Command line configuration. */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+#undef CONFIG_CMD_PCI
+#undef CONFIG_PCI
+
+#define CONFIG_BOOTCOMMAND		"run boot_flash"
+/* enable passing of ATAGs */
+#define CONFIG_CMDLINE_TAG		1
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+#define CONFIG_REVISION_TAG		1
+
+#if defined(CONFIG_CMD_KGDB)
+# define CONFIG_KGDB_BAUDRATE		230400
+/* which serial port to use */
+# define CONFIG_KGDB_SER_INDEX		1
+#endif
+
+/* Miscellaneous configurable options */
+#define CFG_LONGHELP
+#define CFG_PROMPT			"=> "
+/* Console I/O Buffer Size */
+#define CFG_CBSIZE			256
+/* Print Buffer Size */
+#define CFG_PBSIZE			(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+/* max number of command args */
+#define CFG_MAXARGS			16
+/* Boot Argument Buffer Size */
+#define CFG_BARGSIZE			CFG_CBSIZE
+
+#define CFG_MEMTEST_START		0x00400000
+#define CFG_MEMTEST_END			0x00800000
+
+/* everything, incl board info, in Hz */
+#undef  CFG_CLKS_IN_HZ
+/* spec says 66.666 MHz, but it appears to be 33 */
+#define CFG_HZ				3333333
+
+/* default load address */
+#define CFG_LOAD_ADDR			0x00010000
+
+/* valid baudrates */
+#define CFG_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, \
+					  115200, 230400 }
+#define CONFIG_SERIAL_RTS_ACTIVE	1
+
+/*
+ * Stack sizes
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE		(128*1024)	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+# define CONFIG_STACKSIZE_IRQ		(4*1024)	/* IRQ stack */
+# define CONFIG_STACKSIZE_FIQ		(4*1024)	/* FIQ stack */
+#endif
+
+/* Expansion bus settings */
+#define CFG_EXP_CS0			0xbd113042
+
+/* SDRAM settings */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM_1			0x00000000
+#define CFG_DRAM_BASE			0x00000000
+
+/* 16MB SDRAM */
+#define CFG_SDR_CONFIG			0x3A
+#define PHYS_SDRAM_1_SIZE		0x01000000
+#define CFG_SDRAM_REFRESH_CNT		0x81a
+#define CFG_SDR_MODE_CONFIG		0x1
+#define CFG_DRAM_SIZE			0x01000000
+
+/* FLASH organization */
+#define CFG_MAX_FLASH_BANKS		1
+/* max number of sectors on one chip */
+#define CFG_MAX_FLASH_SECT		140
+#define PHYS_FLASH_1			0x50000000
+#define CFG_FLASH_BANKS_LIST		{ PHYS_FLASH_1 }
+
+#define CFG_FLASH_BASE			PHYS_FLASH_1
+#define CFG_MONITOR_BASE		PHYS_FLASH_1
+#define CFG_MONITOR_LEN			(256 << 10)
+
+/* Use common CFI driver */
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+/* no byte writes on IXP4xx */
+#define CFG_FLASH_CFI_WIDTH		FLASH_CFI_16BIT
+
+/* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_EMPTY_INFO
+
+/* Ethernet */
+
+/* include IXP4xx NPE support */
+#define CONFIG_IXP4XX_NPE		1
+/* use separate flash sector with ucode images */
+#define CONFIG_IXP4XX_NPE_EXT_UCODE_BASE	0x50040000
+#define CONFIG_NET_MULTI		1
+/* NPE0 PHY address */
+#define	CONFIG_PHY_ADDR			0x00
+/* MII PHY management */
+#define CONFIG_MII			1
+/* Number of ethernet rx buffers & descriptors */
+#define CFG_RX_ETH_BUFFER		16
+#define CONFIG_RESET_PHY_R		1
+/* ethernet switch connected to MII port */
+#define CONFIG_MII_ETHSWITCH		1
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#undef  CONFIG_CMD_NFS
+
+/* BOOTP options */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/* Cache Configuration */
+#define CFG_CACHELINE_SIZE		32
+
+/*
+ * environment organization:
+ * one flash sector, embedded in uboot area (bottom bootblock flash)
+ */
+#define	CFG_ENV_IS_IN_FLASH		1
+#define CFG_ENV_SIZE			0x2000
+#define CFG_ENV_ADDR			(PHYS_FLASH_1 + 0x4000)
+#define CFG_USE_PPCENV			1
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \
+	"kerneladdr=50050000\0"						\
+	"rootaddr=50170000\0"						\
+	"loadaddr=10000\0"						\
+	"updateboot_ser=mw.b 10000 ff 40000;"				\
+	" loady ${loadaddr};"						\
+	" run eraseboot writeboot\0"					\
+	"updateboot_net=mw.b 10000 ff 40000;"				\
+	" tftp ${loadaddr} u-boot.bin;"					\
+	" run eraseboot writeboot\0"					\
+	"eraseboot=protect off 50000000 50003fff;"			\
+	" protect off 50006000 5003ffff;"				\
+	" erase 50000000 50003fff;"					\
+	" erase 50006000 5003ffff\0"					\
+	"writeboot=cp.b 10000 50000000 4000;"				\
+	" cp.b 16000 50006000 3a000\0"					\
+	"eraseenv=protect off 50004000 50005fff;"			\
+	" erase 50004000 50005fff\0"					\
+	"updateroot=tftp ${loadaddr} ${rootfile};"			\
+	" era ${rootaddr} +${filesize};"				\
+	" cp.b ${loadaddr} ${rootaddr} ${filesize}\0"			\
+	"updatekern=tftp ${loadaddr} ${kernelfile};"			\
+	" era ${kerneladdr} +${filesize};"				\
+	" cp.b ${loadaddr} ${kerneladdr} ${filesize}\0"			\
+	"flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3"	\
+	" rootfstype=squashfs,jffs2 init=/etc/preinit\0"		\
+	"netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3"	\
+	" rootfstype=squashfs,jffs2 init=/etc/preinit\0"		\
+	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
+	"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0"	\
+	"boot_flash=run flashargs addtty addeth;"			\
+	" bootm ${kerneladdr}\0"					\
+	"boot_net=run netargs addtty addeth;"				\
+	" tftpboot ${loadaddr} ${kernelfile};"				\
+	" bootm\0"
+
+#endif /* __CONFIG_H */