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Commit aa7a2226 authored by Shengzhou Liu's avatar Shengzhou Liu Committed by York Sun
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armv8/ls2080ardb: Update DDR timing to support more UDIMMs


Optimize DDR timing for good margins to support new Transcend
and Apacer DDR4 UDIMM besides current Micron UDIMM.

Verified 1333MT/s, 1600MT/s, 1866MT/s, 2133MT/s rate with
following UDIMM on LS2080ARDB.
 - Micron UDIMM: MTA18ASF1G72AZ-2G1A1Z
 - Apacer UDIMM: 78.C1GM4.AF10B
 - Transcend UDIMM: TS1GLH72V1H

Signed-off-by: default avatarShengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: default avatarYork Sun <york.sun@nxp.com>
parent 5fc62fe5
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