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Commit a8b8df29 authored by Troy Kisky's avatar Troy Kisky
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nitrogen8m: port to v2018.07

parent 8de3b8e4
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......@@ -143,8 +143,6 @@ int ft_board_setup(void *blob, bd_t *bd)
#define STRAP_AR8035 ((0x28 | (CONFIG_FEC_MXC_PHYADDR & 3)) | ((0x28 | ((CONFIG_FEC_MXC_PHYADDR + 1) & 3)) << 6))
#endif
#define IOMUX_PAD_CTRL(name, ctrl) NEW_PAD_CTRL(IMX8MQ_PAD_##name, ctrl)
static const iomux_v3_cfg_t enet_ar8035_gpio_pads[] = {
#define GP_RGMII_PHY_RESET IMX_GPIO_NR(1, 9)
IOMUX_PAD_CTRL(GPIO1_IO09__GPIO1_IO9, PAD_CTL_DSE6),
......
......@@ -75,8 +75,9 @@ static iomux_v3_cfg_t const usdhc1_pads[] = {
IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC1_BASE_ADDR, 0, 8},
static struct fsl_esdhc_cfg usdhc_cfg[] = {
{.esdhc_base = USDHC1_BASE_ADDR, .bus_width = 8,
.gp_reset = GP_EMMC_RESET},
};
int board_mmc_init(bd_t *bis)
......
......@@ -49,9 +49,13 @@ CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DM_ETH=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
CONFIG_NETDEVICES=y
CONFIG_FEC_MXC=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_DM_REGULATOR=y
......@@ -66,10 +70,19 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Boundary"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
CONFIG_USBNET_DEVADDR="00:19:b8:00:00:02"
CONFIG_USBNET_HOST_ADDR="00:19:b8:00:00:01"
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_VIDEO=y
CONFIG_VIDEO_IMXDCSS=y
CONFIG_VIDEO_IMX8_HDMI=y
......@@ -74,18 +74,15 @@
/* ENET1 */
#if defined(CONFIG_CMD_NET)
#define CONFIG_MII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_FEC_MXC_PHYADDR 4
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_FEC_MXC_PHYADDR 4
#define FEC_QUIRK_ENET_MAC
#define CONFIG_PHY_GIGE
#define IMX_FEC_BASE 0x30BE0000
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS
#endif
/* Link Definitions */
......@@ -128,7 +125,6 @@
#define CONFIG_IMX_BOOTAUX
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_USDHC_NUM 1
......
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