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Commit a4b6358a authored by Troy Kisky's avatar Troy Kisky
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nitrogen8m: use common ddrphy_train 


Signed-off-by: default avatarTroy Kisky <troy.kisky@boundarydevices.com>
parent 5fe10a00
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board/boundary/nitrogen8m/Makefile
+ 1
− 1
View file @ a4b6358a
......@@ -9,5 +9,5 @@ obj-y += nitrogen8m.o mmc.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
obj-y += lpddr4_timing.o
obj-y += ddr/ddr_init.o ddr/ddrphy_train.o ddr/lpddr4_timing.o
obj-y += ddr/ddr_init.o ddr/lpddr4_timing.o
endif
board/boundary/nitrogen8m/ddr/ddr.h
+ 0
− 6
View file @ a4b6358a
......@@ -7,9 +7,3 @@
void ddr_init1(struct dram_timing_info *dram_timing);
extern struct dram_timing_info lpddr4_timing_;
void lpddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num);
void lpddr4_800M_cfg_phy(struct dram_timing_info *dram_timing);
static inline void reg32_writep(u32 *addr, u32 val)
{
writel(val, addr);
}
board/boundary/nitrogen8m/ddr/ddr_init.c
+ 3
− 3
View file @ a4b6358a
......@@ -40,8 +40,8 @@ void ddr_init1(struct dram_timing_info *dram_timing)
reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000);
/* change the clock source of dram_apb_clk_root */
reg32_writep(&ccm_reg->ip_root[1].target_root_clr, (0x7<<24)|(0x7<<16));
reg32_writep(&ccm_reg->ip_root[1].target_root_set, (0x4<<24)|(0x3<<16));
writel((0x7<<24)|(0x7<<16), &ccm_reg->ip_root[1].target_root_clr);
writel((0x4<<24)|(0x3<<16), &ccm_reg->ip_root[1].target_root_set); /* to source 4 --800MHz/4 */
/* disable iso */
reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */
......@@ -85,7 +85,7 @@ void ddr_init1(struct dram_timing_info *dram_timing)
reg32_write(DDRC_DFIMISC(0), 0x00000010);
#endif
/* LPDDR4 PHY config and training */
lpddr4_800M_cfg_phy(dram_timing);
ddr_cfg_phy(dram_timing);
reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
......
board/boundary/nitrogen8m/ddr/ddrphy_train.c deleted 100644 → 0
+ 0
− 160
View file @ 5fe10a00
/*
* Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/ddr.h>
#include <asm/arch/imx8m_ddr.h>
#include "ddr_memory_map.h"
#include "ddr.h"
#include "lpddr4_dvfs.h"
extern void wait_ddrphy_training_complete(void);
void sscgpll_bypass_enable(unsigned int reg_addr)
{
unsigned int read_data;
read_data = reg32_read(reg_addr);
reg32_write(reg_addr, read_data | 0x00000010);
read_data = reg32_read(reg_addr);
reg32_write(reg_addr, read_data | 0x00000020);
}
void sscgpll_bypass_disable(unsigned int reg_addr)
{
unsigned int read_data;
read_data = reg32_read(reg_addr);
reg32_write(reg_addr, read_data & 0xffffffdf);
read_data = reg32_read(reg_addr);
reg32_write(reg_addr, read_data & 0xffffffef);
}
unsigned int wait_pll_lock(unsigned int reg_addr)
{
unsigned int pll_lock;
pll_lock = reg32_read(reg_addr) >> 31;
return pll_lock;
}
void ddr_pll_config_freq(unsigned int freq)
{
unsigned int ddr_pll_lock = 0x0;
sscgpll_bypass_enable(HW_DRAM_PLL_CFG0_ADDR);
switch (freq) {
case 800:
reg32_write(HW_DRAM_PLL_CFG2_ADDR, 0x00ece580);
break;
case 700:
reg32_write(HW_DRAM_PLL_CFG2_ADDR, 0x00ec4580);
break;
case 667:
reg32_write(HW_DRAM_PLL_CFG2_ADDR, 0x00ece480);
break;
case 400:
reg32_write(HW_DRAM_PLL_CFG2_ADDR, 0x00ec6984);
break;
case 167:
reg32_write(HW_DRAM_PLL_CFG2_ADDR, 0x00f5a406);
break;
case 100:
reg32_write(HW_DRAM_PLL_CFG2_ADDR, 0x015dea96);
break;
default:
printf("Input freq=%d error.\n",freq);
}
sscgpll_bypass_disable(HW_DRAM_PLL_CFG0_ADDR);
while (ddr_pll_lock != 0x1) {
ddr_pll_lock = wait_pll_lock(HW_DRAM_PLL_CFG0_ADDR);
}
}
void dwc_ddrphy_phyinit_userCustom_E_setDfiClk(int pstate)
{
struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR;
if (pstate == 0x1) {
reg32_writep(&ccm_reg->ip_root[1].target_root_clr, (0x7<<24)|(0x7<<16));
reg32_writep(&ccm_reg->ip_root[1].target_root_set, (0x4<<24)|(0x4<<16)); /* to source 4 --800MHz/5 */
ddr_pll_config_freq(167);
} else {
ddr_pll_config_freq(800);
reg32_writep(&ccm_reg->ip_root[1].target_root_clr, (0x7<<24)|(0x7<<16));
reg32_writep(&ccm_reg->ip_root[1].target_root_set, (0x4<<24)|(0x3<<16)); /* to source 4 --800MHz/4 */
}
}
static void dwc_ddrphy_apb_wr_list(struct dram_cfg_param *dram_cfg, int cnt)
{
int i;
for (i = 0; i < cnt; i++) {
dwc_ddrphy_apb_wr(dram_cfg->reg, dram_cfg->val);
dram_cfg++;
}
}
void lpddr4_800M_cfg_phy(struct dram_timing_info *dram_timing)
{
struct dram_fsp_msg *fsp_msg;
int i = 0;
int drate = 0;
printf("start to config phy: p0=3200mts, p1=667mts with 1D2D training\n");
dwc_ddrphy_apb_wr_list(dram_timing->ddrphy_cfg,
dram_timing->ddrphy_cfg_num);
/* load the frequency setpoint message block config */
fsp_msg = dram_timing->fsp_msg;
for (i = 0; i < dram_timing->fsp_msg_num; i++) {
/* Set the PHY input clocks for pstate */
if (drate != fsp_msg->drate) {
drate = fsp_msg->drate;
dwc_ddrphy_phyinit_userCustom_E_setDfiClk((fsp_msg->drate >= 1600) ? 0 : 1);
dwc_ddrphy_apb_wr(0xd0000, 0x0);
}
dwc_ddrphy_apb_wr(0xd0000, 0x0);
ddr_load_train_firmware(fsp_msg->fw_type);
dwc_ddrphy_apb_wr(0xd0000, 0x1);
printf("config to do %u %ud training.\n", fsp_msg->drate,
fsp_msg->fw_type == FW_1D_IMAGE ? 1 : 2);
/* load the frequency set point message block parameter */
dwc_ddrphy_apb_wr_list(fsp_msg->fsp_cfg, fsp_msg->fsp_cfg_num);
/*
* -------------------- excute the firmware --------------------
* Running the firmware is a simply process to taking the
* PMU out of reset and stall, then the firwmare will be run
* 1. reset the PMU;
* 2. begin the excution;
* 3. wait for the training done;
* 4. read the message block result.
* -------------------------------------------------------------
*/
dwc_ddrphy_apb_wr(0xd0000, 0x1);
dwc_ddrphy_apb_wr(0xd0099, 0x9);
dwc_ddrphy_apb_wr(0xd0099, 0x1);
dwc_ddrphy_apb_wr(0xd0099, 0x0);
/* Wait for the training firmware to complete */
wait_ddrphy_training_complete();
/* Halt the microcontroller. */
dwc_ddrphy_apb_wr(0xd0099, 0x1);
dwc_ddrphy_apb_wr(0xd0000, 0x0);
dwc_ddrphy_apb_wr(0xd0000, 0x1);
fsp_msg++;
}
/* (I) Load PHY Init Engine Image */
printf("Load 201711 PIE\n");
dwc_ddrphy_apb_wr_list(dram_timing->ddrphy_pie, dram_timing->ddrphy_pie_num);
}
board/boundary/nitrogen8m/ddr/lpddr4_dvfs.h deleted 100644 → 0
+ 0
− 78
View file @ 5fe10a00
/*
* Copyright 2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __LPDDR4_DVFS_H__
#define __LPDDR4_DVFS_H__
#include "ddr_memory_map.h"
#define DFILP_SPT
#define ANAMIX_PLL_BASE_ADDR 0x30360000
#define HW_DRAM_PLL_CFG0_ADDR (ANAMIX_PLL_BASE_ADDR + 0x60)
#define HW_DRAM_PLL_CFG1_ADDR (ANAMIX_PLL_BASE_ADDR + 0x64)
#define HW_DRAM_PLL_CFG2_ADDR (ANAMIX_PLL_BASE_ADDR + 0x68)
#define LPDDR4_HDT_CTL_2D 0xC8 /* stage completion */
#define LPDDR4_HDT_CTL_3200_1D 0xC8 /* stage completion */
#define LPDDR4_HDT_CTL_400_1D 0xC8 /* stage completion */
#define LPDDR4_HDT_CTL_100_1D 0xC8 /* stage completion */
/* 2D share & weight */
#define LPDDR4_2D_WEIGHT 0x1f7f
#define LPDDR4_2D_SHARE 1
#define LPDDR4_CATRAIN_3200_1d 0
#define LPDDR4_CATRAIN_400 0
#define LPDDR4_CATRAIN_100 0
#define LPDDR4_CATRAIN_3200_2d 0
#define WR_POST_EXT_3200 /* recommened to define */
/* lpddr4 phy training config */
/* for LPDDR4 Rtt */
#define LPDDR4_RTT40 6
#define LPDDR4_RTT48 5
#define LPDDR4_RTT60 4
#define LPDDR4_RTT80 3
#define LPDDR4_RTT120 2
#define LPDDR4_RTT240 1
#define LPDDR4_RTT_DIS 0
/* for LPDDR4 Ron */
#define LPDDR4_RON34 7
#define LPDDR4_RON40 6
#define LPDDR4_RON48 5
#define LPDDR4_RON60 4
#define LPDDR4_RON80 3
#define LPDDR4_PHY_ADDR_RON60 0x1
#define LPDDR4_PHY_ADDR_RON40 0x3
#define LPDDR4_PHY_ADDR_RON30 0x7
#define LPDDR4_PHY_ADDR_RON24 0xf
#define LPDDR4_PHY_ADDR_RON20 0x1f
/* for read channel */
#define LPDDR4_RON LPDDR4_RON40 /* MR3[5:3] */
#define LPDDR4_PHY_RTT 30
#define LPDDR4_PHY_VREF_VALUE 17
/* for write channel */
#define LPDDR4_PHY_RON 30
#define LPDDR4_PHY_ADDR_RON LPDDR4_PHY_ADDR_RON40
#define LPDDR4_RTT_DQ LPDDR4_RTT40 /* MR11[2:0] */
#define LPDDR4_RTT_CA LPDDR4_RTT40 /* MR11[6:4] */
#define LPDDR4_RTT_CA_BANK0 LPDDR4_RTT40 /* MR11[6:4] */
#define LPDDR4_RTT_CA_BANK1 LPDDR4_RTT40 /* LPDDR4_RTT_DIS//MR11[6:4] */
#define LPDDR4_VREF_VALUE_CA ((1<<6)|(0xd)) /*((0<<6)|(0xe)) MR12 */
#define LPDDR4_VREF_VALUE_DQ_RANK0 ((1<<6)|(0xd)) /* MR14 */
#define LPDDR4_VREF_VALUE_DQ_RANK1 ((1<<6)|(0xd)) /* MR14 */
#define LPDDR4_MR22_RANK0 ((0<<5)|(1<<4)|(0<<3)|(LPDDR4_RTT40)) /* MR22: OP[5:3]ODTD-CA,CS,CK */
#define LPDDR4_MR22_RANK1 ((0<<5)|(1<<4)|(0<<3)|(LPDDR4_RTT40)) /* MR22: OP[5:3]ODTD-CA,CS,CK */
#define LPDDR4_MR3_PU_CAL 1 /* MR3[0] */
#define LPDDR4_2D_WEIGHT 0x1f7f
#define LPDDR4_2D_SHARE 1
#endif /*__LPDDR4_DVFS_H__ */
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