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Commit a2c95a72 authored by Stefan Roese's avatar Stefan Roese
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PPC440 DDR setup: Set SDRAM0_CFG0[PMU]=0 for best performance 

AMCC suggested to set the PMU bit to 0 for best performace on
the PPC440 DDR controller.
Please see doc/README.440-DDR-performance for details.
Patch by Stefan Roese, 28 Jul 2006
parent fc6c4a67
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