Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx

arch/powerpc/cpu/mpc83xx/pcie.c

@@ -48,11 +48,26 @@ static struct {
 
 #ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
 
+/* private structure for mpc83xx pcie hose */
+static struct mpc83xx_pcie_priv {
+	u8 index;
+} pcie_priv[PCIE_MAX_BUSES] = {
+	{
+		/* pcie controller 1 */
+		.index = 0,
+	},
+	{
+		/* pcie controller 2 */
+		.index = 1,
+	},
+};
+
 static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev)
 {
 	int bus = PCI_BUS(dev) - hose->first_busno;
 	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
-	pex83xx_t *pex = &immr->pciexp[bus];
+	struct mpc83xx_pcie_priv *pcie_priv = hose->priv_data;
+	pex83xx_t *pex = &immr->pciexp[pcie_priv->index];
 	struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0];
 	u8 devfn = PCI_DEV(dev) << 3 | PCI_FUNC(dev);
 	u32 dev_base = bus << 24 | devfn << 16;
@@ -142,6 +157,8 @@ static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
 
 	hose->cfg_addr = (unsigned int *)mpc83xx_pcie_cfg_space[bus].base;
 
+	hose->priv_data = &pcie_priv[bus];
+
 	pci_set_ops(hose,
 			pcie_read_config_byte,
 			pcie_read_config_word,

arch/powerpc/cpu/mpc83xx/speed.c

@@ -161,7 +161,7 @@ int get_clocks(void)
 #endif
 	}
 
-	spmf = ((im->reset.rcwl & HRCWL_SPMF) >> HRCWL_SPMF_SHIFT);
+	spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
 	csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
 
 	sccr = im->clk.sccr;
@@ -392,7 +392,7 @@ int get_clocks(void)
 #endif
 
 	lbiu_clk = csb_clk *
-	           (1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
+		   (1 + ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
 	lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
 	switch (lcrr) {
 	case 2:
@@ -406,11 +406,12 @@ int get_clocks(void)
 	}
 
 	mem_clk = csb_clk *
-		  (1 + ((im->reset.rcwl & HRCWL_DDRCM) >> HRCWL_DDRCM_SHIFT));
-	corepll = (im->reset.rcwl & HRCWL_COREPLL) >> HRCWL_COREPLL_SHIFT;
+		  (1 + ((im->clk.spmr & SPMR_DDRCM) >> SPMR_DDRCM_SHIFT));
+	corepll = (im->clk.spmr & SPMR_COREPLL) >> SPMR_COREPLL_SHIFT;
+
 #if defined(CONFIG_MPC8360)
 	mem_sec_clk = csb_clk * (1 +
-		       ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
+		       ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
 #endif
 
 	corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
@@ -442,8 +443,8 @@ int get_clocks(void)
 	}
 
 #if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
-	qepmf = (im->reset.rcwl & HRCWL_CEPMF) >> HRCWL_CEPMF_SHIFT;
-	qepdf = (im->reset.rcwl & HRCWL_CEPDF) >> HRCWL_CEPDF_SHIFT;
+	qepmf = (im->clk.spmr & SPMR_CEPMF) >> SPMR_CEPMF_SHIFT;
+	qepdf = (im->clk.spmr & SPMR_CEPDF) >> SPMR_CEPDF_SHIFT;
 	qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
 	brg_clk = qe_clk / 2;
 #endif

include/mpc83xx.h

@@ -694,14 +694,21 @@
 /* SPMR - System PLL Mode Register
  */
 #define SPMR_LBIUCM			0x80000000
+#define SPMR_LBIUCM_SHIFT		31
 #define SPMR_DDRCM			0x40000000
+#define SPMR_DDRCM_SHIFT		30
 #define SPMR_SPMF			0x0F000000
+#define SPMR_SPMF_SHIFT		24
 #define SPMR_CKID			0x00800000
 #define SPMR_CKID_SHIFT			23
 #define SPMR_COREPLL			0x007F0000
+#define SPMR_COREPLL_SHIFT		16
 #define SPMR_CEVCOD			0x000000C0
+#define SPMR_CEVCOD_SHIFT		6
 #define SPMR_CEPDF			0x00000020
+#define SPMR_CEPDF_SHIFT		5
 #define SPMR_CEPMF			0x0000001F
+#define SPMR_CEPMF_SHIFT		0
 
 /* OCCR - Output Clock Control Register
  */

include/pci.h

@@ -420,6 +420,8 @@ struct pci_controller {
 	/* Used by ppc405 autoconfig*/
 	struct pci_region *pci_fb;
 	int current_busno;
+
+	void *priv_data;
 };
 
 extern __inline__ void pci_set_ops(struct pci_controller *hose,