Skip to content
Snippets Groups Projects
Commit 84777634 authored by Simon Glass's avatar Simon Glass Committed by Tom Rini
Browse files

README: Drop old Intel Monahans comment


This is no longer in the U-Boot source code, so drop this note from the
README.

Signed-off-by: default avatarSimon Glass <sjg@chromium.org>
Reviewed-by: default avatarBin Meng <bmeng.cn@gmail.com>
Reviewed-by: default avatarYork Sun <york.sun@nxp.com>
parent d32b2d1c
No related branches found
No related tags found
No related merge requests found
...@@ -578,20 +578,6 @@ The following options need to be configured: ...@@ -578,20 +578,6 @@ The following options need to be configured:
CONFIG_SYS_FSL_SEC_LE CONFIG_SYS_FSL_SEC_LE
Defines the SEC controller register space as Little Endian Defines the SEC controller register space as Little Endian
- Intel Monahans options:
CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
Defines the Monahans run mode to oscillator
ratio. Valid values are 8, 16, 24, 31. The core
frequency is this value multiplied by 13 MHz.
CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO
Defines the Monahans turbo mode to oscillator
ratio. Valid values are 1 (default if undefined) and
2. The core frequency as calculated above is multiplied
by this value.
- MIPS CPU options: - MIPS CPU options:
CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_INIT_SP_OFFSET
......
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment