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Commit 81b83c9e authored by Stefan Roese's avatar Stefan Roese
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* Patch by Matthias Fuchs, 03 May 2005:

  Added missing variable declaration in cmd_nand.c
  Modified CFG_PCI_PTM1MS in configs/PLU405.h to map 128MB ram
parent dcb2f95a
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...@@ -1218,6 +1218,8 @@ static int nand_write_page (struct nand_chip *nand, ...@@ -1218,6 +1218,8 @@ static int nand_write_page (struct nand_chip *nand,
} }
if (nand->bus16) { if (nand->bus16) {
for (i = 0; i < nand->oobsize; i += 2) { for (i = 0; i < nand->oobsize; i += 2) {
u16 val;
val = READ_NAND (nand->IO_ADDR); val = READ_NAND (nand->IO_ADDR);
nand->data_buf[i] = val & 0xff; nand->data_buf[i] = val & 0xff;
nand->data_buf[i + 1] = val >> 8; nand->data_buf[i + 1] = val >> 8;
......
...@@ -212,7 +212,7 @@ ...@@ -212,7 +212,7 @@
#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ #define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ #define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ #define CFG_PCI_PTM1MS 0xf8000001 /* 128MB, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ #define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ #define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
......
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