mx6_r: initial addition, Boundary Devices board

mx6_r.h: CONFIG_IPUV3_CLK 264000000
mx6_r: add CONFIG_CMD_GPIO
mx6_r: explicit fbp_detect_i2c
mx6_r: use VDF_LB043
mx6_r: verify port in board_ehci_hcd_init
mx6_r: use boundary.h
mx6_r: setup rgb_gpio_pads in board_early_init_f
mx6_r: add CONFIG_SPI_FLASH_SPANSION
mx6_r: mx6_r_defconfig add CONFIG_BLOCK_CACHE
mx6_r: use common code for eth init
mx6_r: eth.c now in common directory
mx6_r: move misc_init_r/do_kbd to common
mx6_r: move mmc_init/ dram_init/ overwrite_console/ common_board_init/ splash_screen_prepare/ board_cfb_skip to common
mx6_r: add  CONFIG_SPI_FLASH_GIGADEVICE: to defconfigs
mx6_r: add mx6_r_q2g.cfg
mx6_r: port to v2018.07

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>

mx6_r: update to v2017.01
mx6_r: update to v2017.03

Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>

arch/arm/mach-imx/mx6/Kconfig

@@ -440,6 +440,9 @@ config TARGET_MED
 config TARGET_MTP
 	bool "mtp"
 
+config TARGET_MX6_R
+	bool "mx6_r"
+
 config TARGET_NITROGEN6X
 	bool "nitrogen6x"
 	imply USB_HOST_ETHER
@@ -609,6 +612,7 @@ source "board/boundary/ltch/Kconfig"
 source "board/boundary/mcs/Kconfig"
 source "board/boundary/med/Kconfig"
 source "board/boundary/mtp/Kconfig"
+source "board/boundary/mx6_r/Kconfig"
 source "board/boundary/nitrogen6x/Kconfig"
 source "board/boundary/ys/Kconfig"
 source "board/bticino/mamoj/Kconfig"

board/boundary/mx6_r/6x_bootscript-yocto.txt

+# Yocto-specifics
+setenv bootpart 2
+setenv bootdir /
+
+if ${fs}load mmc ${disk}:1 10008000 logo.bmp.gz ; then
+	bmp d 10008000
+fi
+
+setenv bootargs enable_wait_mode=off
+
+setenv i2cres rtcerr
+if i2c dev 2 ; then
+	if i2c read 0x6f 0.1 6 0x10004000 ; then
+		mw.b 10004006 0 6
+		if cmp.b 10004000 10004006 6 ; then
+			echo "RTC not programmed" ;
+			if i2c mw 0x6f 7.1 0x90 ; then
+				if i2c mw 0x6f 0.1 0x04 6 ; then
+					echo "Initialized RTC" ;
+					setenv i2cres rtcinit ;
+				else
+					setenv i2cres rtcerr-fill
+				fi
+			else
+				setenv i2cres rtcerr-wrinit
+			fi
+		else
+			echo "non-blank RTC data";
+			setenv i2cres rtcok ;
+		fi
+	else
+		setenv i2cres rtcerr-read
+	fi
+else
+	setenv i2cres rtcerr-dev
+fi
+setenv bootargs $bootargs $i2cres
+setenv i2cres
+
+setenv nextcon 0;
+setenv bootargs $bootargs video=mxcfb0:dev=lcd,LB043,if=RGB24
+setenv bootargs $bootargs ft5x06_ts.screenres=800,1280
+# rotate touch coordinates 90 degrees clockwise
+setenv bootargs $bootargs ft5x06_ts.calibration=0,-40928,31391744,40941,0,0,65536
+setenv bootargs $bootargs g_ether.dev_addr=55:aa:55:aa:55:aa
+setenv bootargs $bootargs video=mxcfb1:dev=hdmi,1280x720M@60 video=mxcfb2:off video=mxcfb3:off
+setenv fbmem 28M
+setenv nextcon 1
+
+i2c dev 1 ;
+if i2c probe 0x50 ; then
+	setenv bootargs $bootargs video=mxcfb1:dev=hdmi,1280x720M@60 video=mxcfb2:off video=mxcfb3:off
+	setenv fbmem $fbmem,28M
+	setexpr nextcon $nextcon + 1
+else
+	echo "------ no HDMI monitor";
+fi
+
+while test "4" -ne $nextcon ; do
+	setenv bootargs $bootargs video=mxcfb${nextcon}:off ;
+	setexpr nextcon $nextcon + 1 ;
+done
+
+setenv bootargs $bootargs $fbmem
+setenv bootargs "$bootargs console=ttymxc1,115200 vmalloc=400M consoleblank=0 rootwait"
+
+if itest.s x$bootpart == x ; then
+	bootpart=1
+fi
+
+if test "sata" = "${dtype}" ; then
+	setenv bootargs "$bootargs root=/dev/sda$bootpart" ;
+else
+	setenv bootargs "$bootargs root=/dev/mmcblk0p$bootpart" ;
+fi
+
+dtbname="imx6";
+if itest.s x6S != "x$cpu" ; then
+	dtbname=${dtbname}q-;
+else
+	dtbname=${dtbname}s-;
+fi
+
+if itest.s x == "x$board" ; then
+	board=sabrelite
+fi
+dtbname=${dtbname}${board}.dtb;
+
+if itest.s x == x${bootdir} ; then
+	bootdir=/boot/
+fi
+
+if ${fs}load ${dtype} ${disk}:1 12000000 ${bootdir}$dtbname ; then
+	havedtb=1;
+	setenv fdt_addr 0x11000000
+	setenv fdt_high 0xffffffff
+else
+	havedtb=
+fi
+
+if itest.s x == x$allow_noncea ; then
+	setenv bootargs $bootargs mxc_hdmi.only_cea=1;
+	echo "only CEA modes allowed on HDMI port";
+else
+        setenv bootargs $bootargs mxc_hdmi.only_cea=0;
+        echo "non-CEA modes allowed on HDMI, audio may be affected";
+fi
+
+if kbd ; then
+	if itest.s xD == x$keybd ; then
+		if ${fs}load ${dtype} ${disk}:1 10800000 ${bootdir}uImage-usbwrite ; then
+			if ${fs}load ${dtype} ${disk}:1 12800000 ${bootdir}uramdisk-usbwrite.img ; then
+			   if itest.s x$havedtb == x ; then
+					bootm 10800000 12800000 ;
+			   else
+					bootm 10800000 12800000 12000000 ;
+			   fi
+			fi
+		fi
+	fi
+fi
+
+if ${fs}load ${dtype} ${disk}:1 10800000 ${bootdir}uImage ; then
+	if itest.s x$havedtb == x ; then
+		bootm 10800000 ;
+	else
+		bootm 10800000 - 12000000
+	fi
+fi
+echo "Error loading kernel image"

board/boundary/mx6_r/6x_bootscript.txt

+if ${fs}load mmc ${disk}:1 10008000 logo.bmp.gz ; then
+	bmp d 10008000
+fi
+
+setenv bootargs enable_wait_mode=off
+
+setenv i2cres rtcerr
+if i2c dev 2 ; then
+	if i2c read 0x6f 0.1 6 0x10004000 ; then
+		mw.b 10004006 0 6
+		if cmp.b 10004000 10004006 6 ; then
+			echo "RTC not programmed" ;
+			if i2c mw 0x6f 7.1 0x90 ; then
+				if i2c mw 0x6f 0.1 0x04 6 ; then
+					echo "Initialized RTC" ;
+					setenv i2cres rtcinit ;
+				else
+					setenv i2cres rtcerr-fill
+				fi
+			else
+				setenv i2cres rtcerr-wrinit
+			fi
+		else
+			echo "non-blank RTC data";
+			setenv i2cres rtcok ;
+		fi
+	else
+		setenv i2cres rtcerr-read
+	fi
+else
+	setenv i2cres rtcerr-dev
+fi
+setenv bootargs $bootargs $i2cres
+setenv i2cres
+
+setenv nextcon 0;
+setenv bootargs $bootargs video=mxcfb0:dev=lcd,LB043,if=RGB24
+setenv bootargs $bootargs ft5x06_ts.screenres=800,1280
+# rotate touch coordinates 90 degrees clockwise
+setenv bootargs $bootargs ft5x06_ts.calibration=0,-40928,31391744,40941,0,0,65536
+setenv bootargs $bootargs g_ether.dev_addr=55:aa:55:aa:55:aa
+setenv bootargs $bootargs video=mxcfb1:dev=hdmi,1280x720M@60 video=mxcfb2:off video=mxcfb3:off
+setenv fbmem 28M
+setenv nextcon 1
+
+i2c dev 1 ;
+if i2c probe 0x50 ; then
+	setenv bootargs $bootargs video=mxcfb1:dev=hdmi,1280x720M@60 video=mxcfb2:off video=mxcfb3:off
+	setenv fbmem $fbmem,28M
+	setexpr nextcon $nextcon + 1
+else
+	echo "------ no HDMI monitor";
+fi
+
+while test "4" -ne $nextcon ; do
+	setenv bootargs $bootargs video=mxcfb${nextcon}:off ;
+	setexpr nextcon $nextcon + 1 ;
+done
+
+setenv bootargs $bootargs $fbmem
+setenv bootargs "$bootargs console=ttymxc1,115200 vmalloc=400M consoleblank=0 rootwait"
+
+if itest.s x$bootpart == x ; then
+	bootpart=1
+fi
+
+if test "sata" = "${dtype}" ; then
+	setenv bootargs "$bootargs root=/dev/sda$bootpart" ;
+else
+	setenv bootargs "$bootargs root=/dev/mmcblk0p$bootpart" ;
+fi
+
+dtbname="imx6";
+if itest.s x6S != "x$cpu" ; then
+	dtbname=${dtbname}q-;
+else
+	dtbname=${dtbname}s-;
+fi
+
+if itest.s x == "x$board" ; then
+	board=sabrelite
+fi
+dtbname=${dtbname}${board}.dtb;
+
+if itest.s x == x${bootdir} ; then
+	bootdir=/boot/
+fi
+
+if ${fs}load ${dtype} ${disk}:1 12000000 ${bootdir}$dtbname ; then
+	havedtb=1;
+	setenv fdt_addr 0x11000000
+	setenv fdt_high 0xffffffff
+else
+	havedtb=
+fi
+
+if itest.s x == x$allow_noncea ; then
+	setenv bootargs $bootargs mxc_hdmi.only_cea=1;
+	echo "only CEA modes allowed on HDMI port";
+else
+        setenv bootargs $bootargs mxc_hdmi.only_cea=0;
+        echo "non-CEA modes allowed on HDMI, audio may be affected";
+fi
+
+if kbd ; then
+	if itest.s xD == x$keybd ; then
+		if ${fs}load ${dtype} ${disk}:1 10800000 ${bootdir}uImage-usbwrite ; then
+			if ${fs}load ${dtype} ${disk}:1 12800000 ${bootdir}uramdisk-usbwrite.img ; then
+			   if itest.s x$havedtb == x ; then
+					bootm 10800000 12800000 ;
+			   else
+					bootm 10800000 12800000 12000000 ;
+			   fi
+			fi
+		fi
+	fi
+fi
+
+if ${fs}load ${dtype} ${disk}:1 10800000 ${bootdir}uImage ; then
+	if itest.s x$havedtb == x ; then
+		bootm 10800000 ;
+	else
+		bootm 10800000 - 12000000
+	fi
+fi
+echo "Error loading kernel image"

board/boundary/mx6_r/Kconfig

+if TARGET_MX6_R
+
+config SYS_CPU
+	default "armv7"
+
+config SYS_BOARD
+	default "mx6_r"
+
+config SYS_VENDOR
+	default "boundary"
+
+config SYS_SOC
+	default "mx6"
+
+config SYS_CONFIG_NAME
+	default "mx6_r"
+
+source "board/boundary/common/Kconfig"
+
+endif

board/boundary/mx6_r/MAINTAINERS

+MX6_R BOARD
+M:	Troy Kisky <troy.kisky@boundarydevices.com>
+S:	Maintained
+F:	board/boundary/mx6_r/
+F:	include/configs/mx6_r.h
+F:	configs/mx6_r_defconfig
+

board/boundary/mx6_r/Makefile

+#
+# Copyright (C) 2012-2013, Guennadi Liakhovetski <lg@denx.de>
+# (C) Copyright 2012-2013 Freescale Semiconductor, Inc.
+# Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := mx6_r.o

board/boundary/mx6_r/mx6_r.c

+/*
+ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+#include <malloc.h>
+#include <asm/arch/mx6-pins.h>
+#include <linux/errno.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/fbpanel.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/spi.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <i2c.h>
+#include <spi.h>
+#include <input.h>
+#include <splash.h>
+#include <usb/ehci-ci.h>
+#include "../common/bd_common.h"
+#include "../common/padctrl.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
+	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define RGB_PAD_CTRL	PAD_CTL_DSE_120ohm
+
+#define SPI_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_SPEED_MED |	\
+	PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
+
+#define UART_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+
+#define USDHC_PAD_CTRL	(PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+
+/*
+ *
+ */
+static const iomux_v3_cfg_t init_pads[] = {
+	/* bt_rfkill */
+#define GP_BT_RFKILL_RESET	IMX_GPIO_NR(6, 16)
+	IOMUX_PAD_CTRL(NANDF_CS3__GPIO6_IO16, WEAK_PULLDN),
+
+	/* ECSPI1 */
+	IOMUX_PAD_CTRL(EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL),
+	IOMUX_PAD_CTRL(EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
+	IOMUX_PAD_CTRL(EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL),
+#define GP_ECSPI1_NOR_CS	IMX_GPIO_NR(3, 19)
+	IOMUX_PAD_CTRL(EIM_D19__GPIO3_IO19, WEAK_PULLUP),
+
+	/* ECSPI2 */
+	IOMUX_PAD_CTRL(CSI0_DAT8__ECSPI2_SCLK, SPI_PAD_CTRL),
+	IOMUX_PAD_CTRL(CSI0_DAT9__ECSPI2_MOSI, SPI_PAD_CTRL),
+	IOMUX_PAD_CTRL(CSI0_DAT10__ECSPI2_MISO, SPI_PAD_CTRL),
+#define GP_ECSPI2_CS		IMX_GPIO_NR(5, 29)
+	IOMUX_PAD_CTRL(CSI0_DAT11__GPIO5_IO29, WEAK_PULLUP),
+#define GP_SPI_DISPLAY_RESET	IMX_GPIO_NR(2, 5)
+	IOMUX_PAD_CTRL(NANDF_D5__GPIO2_IO05, WEAK_PULLUP),
+
+	/* gpio_Keys - Button assignments for J14 */
+#define GP_GPIOKEY_BACK		IMX_GPIO_NR(3, 0)
+	IOMUX_PAD_CTRL(EIM_DA0__GPIO3_IO00, WEAK_PULLUP),	/* pin 1 - back */
+#define GP_GPIOKEY_UP		IMX_GPIO_NR(3, 1)
+	IOMUX_PAD_CTRL(EIM_DA1__GPIO3_IO01, WEAK_PULLUP),	/* pin 2 - up */
+#define GP_GPIOKEY_MENU		IMX_GPIO_NR(3, 2)
+	IOMUX_PAD_CTRL(EIM_DA2__GPIO3_IO02, WEAK_PULLUP),	/* pin 3 - Menu */
+#define GP_GPIOKEY_LEFT		IMX_GPIO_NR(3, 3)
+	IOMUX_PAD_CTRL(EIM_DA3__GPIO3_IO03, WEAK_PULLUP),	/* pin 4 - Left */
+#define GP_GPIOKEY_RIGHT	IMX_GPIO_NR(7, 13)
+	IOMUX_PAD_CTRL(GPIO_18__GPIO7_IO13, WEAK_PULLUP),	/* pin 5 - Right */
+#define GP_GPIOKEY_DOWN		IMX_GPIO_NR(4, 5)
+	IOMUX_PAD_CTRL(GPIO_19__GPIO4_IO05, WEAK_PULLUP),	/* pin 6 - Down */
+	IOMUX_PAD_CTRL(KEY_COL2__GPIO4_IO10, WEAK_PULLUP),	/* pin 7 - NC */
+	IOMUX_PAD_CTRL(KEY_ROW2__GPIO4_IO11, WEAK_PULLUP),	/* pin 8 - NC */
+#define GP_GPIOKEY_POWER	IMX_GPIO_NR(6, 1)
+	IOMUX_PAD_CTRL(CSI0_DAT15__GPIO6_IO01, WEAK_PULLDN),	/* pin 9 inverted, Main power off request */
+	IOMUX_PAD_CTRL(NANDF_CS0__GPIO6_IO11, WEAK_PULLUP),	/* pin 10 - NC */
+	IOMUX_PAD_CTRL(SD1_DAT1__GPIO1_IO17, WEAK_PULLUP),	/* pin 11 - NC */
+
+#define GP_MAIN_POWER			IMX_GPIO_NR(1, 16)
+	IOMUX_PAD_CTRL(SD1_DAT0__GPIO1_IO16, OUTPUT_40OHM),
+
+	/* i2c2 ov5640 mipi Camera controls */
+#define GP_OV5640_MIPI_POWER_DOWN	IMX_GPIO_NR(5, 21)
+	IOMUX_PAD_CTRL(CSI0_VSYNC__GPIO5_IO21, OUTPUT_40OHM),
+#define GP_OV5640_MIPI_RESET		IMX_GPIO_NR(5, 20)
+	IOMUX_PAD_CTRL(CSI0_DATA_EN__GPIO5_IO20, OUTPUT_40OHM),
+
+#define GP_LED			IMX_GPIO_NR(3, 20)
+	IOMUX_PAD_CTRL(EIM_D20__GPIO3_IO20, OUTPUT_40OHM),
+	/* BAT status */
+	IOMUX_PAD_CTRL(NANDF_D2__GPIO2_IO02, WEAK_PULLUP),
+
+	/* Misc outputs */
+#define GP_L1			IMX_GPIO_NR(1, 3)
+	IOMUX_PAD_CTRL(GPIO_3__GPIO1_IO03, OUTPUT_40OHM),
+
+#define GP_L2			IMX_GPIO_NR(3, 29)
+	IOMUX_PAD_CTRL(EIM_D29__GPIO3_IO29, OUTPUT_40OHM),
+
+	/* PWM1 - Backlight on RGB connector: J15 */
+#define GP_BACKLIGHT_RGB	IMX_GPIO_NR(1, 21)
+	IOMUX_PAD_CTRL(SD1_DAT3__GPIO1_IO21, WEAK_PULLDN),
+
+	/* reg 3.3v */
+#define GP_REG_3P3V		IMX_GPIO_NR(2, 26)
+	IOMUX_PAD_CTRL(EIM_RW__GPIO2_IO26, OUTPUT_40OHM),
+
+	/* reg 5v */
+#define GP_REG_5V		IMX_GPIO_NR(6, 9)
+	IOMUX_PAD_CTRL(NANDF_WP_B__GPIO6_IO09, OUTPUT_40OHM),
+
+	/* reg 5.4v */
+#define GP_REG_5P4V		IMX_GPIO_NR(2, 1)
+	IOMUX_PAD_CTRL(NANDF_D1__GPIO2_IO01, OUTPUT_40OHM),
+
+	/* reg_usbotg_vbus */
+#define GP_REG_USBOTG		IMX_GPIO_NR(3, 22)
+	IOMUX_PAD_CTRL(EIM_D22__GPIO3_IO22, WEAK_PULLDN),
+
+	/* reg_wlan_en */
+#define GP_REG_WLAN_EN		IMX_GPIO_NR(6, 15)
+	IOMUX_PAD_CTRL(NANDF_CS2__GPIO6_IO15, WEAK_PULLDN),
+
+	/* UART1 */
+	IOMUX_PAD_CTRL(SD3_DAT6__UART1_RX_DATA, UART_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD3_DAT7__UART1_TX_DATA, UART_PAD_CTRL),
+
+	/* UART2 */
+	IOMUX_PAD_CTRL(EIM_D26__UART2_TX_DATA, UART_PAD_CTRL),
+	IOMUX_PAD_CTRL(EIM_D27__UART2_RX_DATA, UART_PAD_CTRL),
+
+	/* USBH1 */
+#define GP_USB_HUB_RESET	IMX_GPIO_NR(7, 12)
+	IOMUX_PAD_CTRL(GPIO_17__GPIO7_IO12, WEAK_PULLDN),
+
+	/* USDHC2 - TiWi wl1271 */
+	IOMUX_PAD_CTRL(SD2_CLK__SD2_CLK, USDHC_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD2_CMD__SD2_CMD, USDHC_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD2_DAT0__SD2_DATA0, USDHC_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD2_DAT1__SD2_DATA1, USDHC_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD2_DAT2__SD2_DATA2, USDHC_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD2_DAT3__SD2_DATA3, USDHC_PAD_CTRL),
+
+	/* USDHC3 - eMMC */
+	IOMUX_PAD_CTRL(SD3_CLK__SD3_CLK, USDHC_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD3_CMD__SD3_CMD, USDHC_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD3_DAT4__SD3_DATA4, USDHC_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD3_DAT5__SD3_DATA5, USDHC_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD3_DAT6__SD3_DATA6, USDHC_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD3_DAT7__SD3_DATA7, USDHC_PAD_CTRL),
+
+	/* USDHC4 - sdcard */
+	IOMUX_PAD_CTRL(SD4_CLK__SD4_CLK, USDHC_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD4_CMD__SD4_CMD, USDHC_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD4_DAT0__SD4_DATA0, USDHC_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD4_DAT1__SD4_DATA1, USDHC_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD4_DAT2__SD4_DATA2, USDHC_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD4_DAT3__SD4_DATA3, USDHC_PAD_CTRL),
+#define GP_USDHC4_CD		IMX_GPIO_NR(4, 20)
+	IOMUX_PAD_CTRL(DI0_PIN4__GPIO4_IO20, NO_PAD_CTRL), /* CD */
+
+	/* wl1271 */
+#define GPIRQ_WL1271_WL		IMX_GPIO_NR(6, 14)
+	IOMUX_PAD_CTRL(NANDF_CS1__GPIO6_IO14, WEAK_PULLDN),
+};
+
+#ifdef CONFIG_CMD_FBPANEL
+static iomux_v3_cfg_t const rgb_pads[] = {
+	IOMUX_PAD_CTRL(DI0_DISP_CLK__IPU1_DI0_DISP_CLK, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DI0_PIN15__IPU1_DI0_PIN15, RGB_PAD_CTRL),	/* DRDY */
+	IOMUX_PAD_CTRL(DI0_PIN2__IPU1_DI0_PIN02, RGB_PAD_CTRL),		/* HSYNC */
+	IOMUX_PAD_CTRL(DI0_PIN3__IPU1_DI0_PIN03, RGB_PAD_CTRL),		/* VSYNC */
+	IOMUX_PAD_CTRL(DISP0_DAT0__IPU1_DISP0_DATA00, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT1__IPU1_DISP0_DATA01, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT2__IPU1_DISP0_DATA02, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT3__IPU1_DISP0_DATA03, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT4__IPU1_DISP0_DATA04, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT5__IPU1_DISP0_DATA05, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT6__IPU1_DISP0_DATA06, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT7__IPU1_DISP0_DATA07, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT8__IPU1_DISP0_DATA08, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT9__IPU1_DISP0_DATA09, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT10__IPU1_DISP0_DATA10, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT11__IPU1_DISP0_DATA11, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT12__IPU1_DISP0_DATA12, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT13__IPU1_DISP0_DATA13, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT14__IPU1_DISP0_DATA14, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT15__IPU1_DISP0_DATA15, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT16__IPU1_DISP0_DATA16, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT17__IPU1_DISP0_DATA17, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT18__IPU1_DISP0_DATA18, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT19__IPU1_DISP0_DATA19, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT20__IPU1_DISP0_DATA20, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT21__IPU1_DISP0_DATA21, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT22__IPU1_DISP0_DATA22, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT23__IPU1_DISP0_DATA23, RGB_PAD_CTRL),
+};
+#endif
+
+static const iomux_v3_cfg_t rgb_gpio_pads[] = {
+	IOMUX_PAD_CTRL(DI0_DISP_CLK__GPIO4_IO16, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DI0_PIN15__GPIO4_IO17, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DI0_PIN2__GPIO4_IO18, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DI0_PIN3__GPIO4_IO19, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT0__GPIO4_IO21, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT1__GPIO4_IO22, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT2__GPIO4_IO23, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT3__GPIO4_IO24, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT4__GPIO4_IO25, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT5__GPIO4_IO26, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT6__GPIO4_IO27, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT7__GPIO4_IO28, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT8__GPIO4_IO29, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT9__GPIO4_IO30, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT10__GPIO4_IO31, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT11__GPIO5_IO05, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT12__GPIO5_IO06, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT13__GPIO5_IO07, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT14__GPIO5_IO08, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT15__GPIO5_IO09, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT16__GPIO5_IO10, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT17__GPIO5_IO11, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT18__GPIO5_IO12, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT19__GPIO5_IO13, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT20__GPIO5_IO14, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT21__GPIO5_IO15, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT22__GPIO5_IO16, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT23__GPIO5_IO17, WEAK_PULLUP),
+};
+
+static const struct i2c_pads_info i2c_pads[] = {
+	/* I2C1, SGTL5000 */
+	I2C_PADS_INFO_ENTRY(I2C1, EIM_D21, 3, 21, EIM_D28, 3, 28, I2C_PAD_CTRL),
+	/* I2C2 Camera, MIPI */
+	I2C_PADS_INFO_ENTRY(I2C2, KEY_COL3, 4, 12, KEY_ROW3, 4, 13, I2C_PAD_CTRL),
+	/* I2C3, J15 - RGB connector */
+	I2C_PADS_INFO_ENTRY(I2C3, GPIO_5, 1, 05, GPIO_16, 7, 11, I2C_PAD_CTRL),
+};
+#define I2C_BUS_CNT	3
+
+#ifdef CONFIG_USB_EHCI_MX6
+int board_ehci_hcd_init(int port)
+{
+	if (port) {
+		/* Reset USB hub */
+		gpio_direction_output(GP_USB_HUB_RESET, 0);
+		mdelay(2);
+		gpio_set_value(GP_USB_HUB_RESET, 1);
+	}
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg board_usdhc_cfg[] = {
+	{.esdhc_base = USDHC4_BASE_ADDR, .bus_width = 4,
+			.gp_cd = GP_USDHC4_CD},
+	{.esdhc_base = USDHC3_BASE_ADDR, .bus_width = 8,},
+};
+#endif
+
+#ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 0 && cs == 0) ? GP_ECSPI1_NOR_CS : -1;
+}
+#endif
+
+#ifdef CONFIG_CMD_FBPANEL
+#ifdef CONFIG_MXC_SPI_DISPLAY
+static int spi_display_read(struct spi_slave *spi, u8 addr, u8 reg, u8 *data, size_t data_len)
+{
+	u8 cmd[2];
+	int ret;
+
+	cmd[0] = addr;
+	cmd[1] = reg;
+	ret = spi_xfer(spi, 2 * 8, cmd, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
+	if (ret) {
+		debug("%s: Failed to select reg 0x%x, %d\n", __func__, reg, ret);
+		return ret;
+	}
+	udelay(3);
+	cmd[0] = addr | 3;
+	ret = spi_xfer(spi, 1 * 8, cmd, NULL, SPI_XFER_BEGIN);
+	if (ret) {
+		debug("%s: Failed to start read for reg 0x%x, %d\n", __func__, reg, ret);
+		return ret;
+	}
+	ret = spi_xfer(spi, data_len * 8, NULL, data, SPI_XFER_END);
+	if (ret) {
+		debug("%s: Failed to read data for reg 0x%x, %d\n", __func__, reg, ret);
+		return ret;
+	}
+	return ret;
+}
+
+static int spi_display_cmds(struct spi_slave *spi, u8 addr, u8 *cmds)
+{
+	u8 cmd_buf[16];
+	int ret = 0;
+
+	printf("%s\n", __func__);
+	while (*cmds) {
+		u8 reg = *cmds++;
+		size_t len = *cmds++;
+
+		cmd_buf[0] = addr;
+		cmd_buf[1] = reg;
+		ret = spi_xfer(spi, 2 * 8, cmd_buf, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
+		if (ret) {
+			debug("%s: Failed to select reg 0x%x, %d\n", __func__, reg, ret);
+			return ret;
+		}
+		udelay(3);
+		cmd_buf[0] = addr | 2;
+		memcpy(&cmd_buf[1], cmds, len);
+		cmds += len;
+		ret = spi_xfer(spi, (len + 1) * 8, cmd_buf, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
+		if (ret) {
+			debug("%s: Failed to write for reg 0x%x, %d\n", __func__, reg, ret);
+			return ret;
+		}
+	}
+	return ret;
+}
+
+static u8 display_init_cmds[] = {
+/* Display Mode Setting */
+	0x36, 1, 0x08,
+	0x3a, 1, 0x70,
+	0xb1, 3, 0x0e, 0x28, 0x0a,
+	0xb2, 2, 0x00, 0xc8,
+	0xb3, 1, 0x00,
+	0xb4, 1, 0x04,
+	0xb5, 5, 0x42, 0x10, 0x10, 0x00, 0x20,
+	0xb6, 6, 0x0b, 0x0f, 0x3c, 0x13, 0x13, 0xe8,
+	0xb7, 5, 0x46, 0x06, 0x0c, 0x00, 0x00,
+/* Power Setting */
+	0xc0, 2, 0x01, 0x11,
+	0xc3, 5, 0x07, 0x03, 0x04, 0x04, 0x04,
+	0xc4, 6, 0x12, 0x24, 0x18, 0x18, 0x02, 0x49,
+	0xc5, 1, 0x6f,
+	0xc6, 2, 0x41, 0x63,
+/* Gamma Setting */
+	0xd0, 9, 0x03, 0x07, 0x73, 0x35, 0x00, 0x01, 0x20, 0x00, 0x03,
+	0xd2, 9, 0x03, 0x07, 0x73, 0x35, 0x00, 0x01, 0x20, 0x00, 0x03,
+	0xd4, 9, 0x03, 0x07, 0x73, 0x35, 0x00, 0x01, 0x20, 0x00, 0x03,
+	0xd1, 9, 0x03, 0x07, 0x73, 0x35, 0x00, 0x01, 0x20, 0x00, 0x03,
+	0xd3, 9, 0x03, 0x07, 0x73, 0x35, 0x00, 0x01, 0x20, 0x00, 0x03,
+	0xd5, 9, 0x03, 0x07, 0x73, 0x35, 0x00, 0x01, 0x20, 0x00, 0x03,
+/* Sleep out */
+	0x11, 0,
+	0
+};
+
+static u8 display_on_cmds[] = {
+	0x29, 0,
+	0
+};
+
+static void enable_spi_rgb(struct display_info_t const *dev)
+{
+	unsigned cs_gpio = GP_ECSPI2_CS;
+	struct spi_slave *spi;
+	int ret;
+
+	printf("%s\n", __func__);
+	gpio_direction_output(GP_BACKLIGHT_RGB, 1);
+	gpio_direction_output(cs_gpio, 1);
+
+	enable_spi_clk(1, dev->bus);
+
+	/* Setup spi_slave */
+	spi = spi_setup_slave(dev->bus, cs_gpio << 8, 1000000, SPI_MODE_3);
+	if (!spi) {
+		printf("%s: Failed to set up slave\n", __func__);
+		return;
+	}
+
+	/* Claim spi bus */
+	ret = spi_claim_bus(spi);
+	if (ret) {
+		debug("%s: Failed to claim SPI bus: %d\n", __func__, ret);
+		goto free_bus;
+	}
+
+	/*
+	 * Initialization sequence
+	 * 1. Display Mode Settings
+	 * 2. Power Settings
+	 * 3. Gamma Settings
+	 * 4. Sleep Out
+	 * 5. Wait >= 7 frame
+	 * 6. Display on
+	 */
+	ret = spi_display_cmds(spi, dev->addr, display_init_cmds);
+	if (ret) {
+		printf("%s: Failed to display_init_cmds %d\n", __func__, ret);
+		goto release_bus;
+	}
+	mdelay(200);
+	ret = spi_display_cmds(spi, dev->addr, display_on_cmds);
+	if (ret) {
+		printf("%s: Failed to display_on_cmds %d\n", __func__, ret);
+		goto release_bus;
+	}
+	ret = 1;
+
+	/* Release spi bus */
+release_bus:
+	spi_release_bus(spi);
+free_bus:
+	spi_free_slave(spi);
+	enable_spi_clk(0, dev->bus);
+	return;
+}
+
+/*
+ * Return 1 for successful detection of display
+ */
+static int detect_spi(struct display_info_t const *dev)
+{
+	int ret;
+	unsigned cs_gpio = GP_ECSPI2_CS;
+	unsigned reset_gpio = GP_SPI_DISPLAY_RESET;	/* nandf_d5 */
+	struct spi_slave *spi;
+	u8 data[8];
+
+	printf("%s\n", __func__);
+	gpio_direction_output(cs_gpio, 1);
+	gpio_direction_output(reset_gpio, 1);
+	udelay(1);
+	gpio_direction_output(reset_gpio, 0);
+	udelay(2000);
+	gpio_direction_output(reset_gpio, 1);
+	udelay(1);
+	enable_spi_clk(1, dev->bus);
+
+	/* Setup spi_slave */
+	spi = spi_setup_slave(dev->bus, cs_gpio << 8, 1000000, SPI_MODE_3);
+	if (!spi) {
+		printf("%s: Failed to set up slave\n", __func__);
+		return 0;
+	}
+
+	/* Claim spi bus */
+	ret = spi_claim_bus(spi);
+	if (ret) {
+		debug("%s: Failed to claim SPI bus: %d\n", __func__, ret);
+		ret = 0;
+		goto free_bus;
+	}
+
+	/* Read the dispctl1 */
+	ret = spi_display_read(spi, dev->addr, 0xb5, data, 2);
+	if (ret) {
+		printf("%s: Failed to read dispctl1, %d\n", __func__, ret);
+		ret = 0;
+		goto release_bus;
+	}
+	debug("%s: *(0x%02x) = 0x%02x 0x%02x\n", __func__, 0xb5, data[0], data[1]);
+
+	if ((data[1] == 0) || (data[1] == 0xff)) {
+		ret = 0;
+		goto release_bus;
+	}
+	/*
+	 * Initialization sequence
+	 * 1. Display Mode Settings
+	 * 2. Power Settings
+	 * 3. Gamma Settings
+	 * 4. Sleep Out
+	 * 5. Wait >= 7 frame
+	 * 6. Display on
+	 */
+	ret = spi_display_cmds(spi, dev->addr, display_init_cmds);
+	if (ret) {
+		printf("%s: Failed to init %d\n", __func__, ret);
+		ret = 0;
+		goto release_bus;
+	}
+	ret = 1;
+
+	/* Release spi bus */
+release_bus:
+	spi_release_bus(spi);
+free_bus:
+	spi_free_slave(spi);
+	enable_spi_clk(0, dev->bus);
+	return ret;
+}
+#endif
+
+void board_enable_lcd(const struct display_info_t *di, int enable)
+{
+	if (enable) {
+		SETUP_IOMUX_PADS(rgb_pads);
+#ifdef CONFIG_MXC_SPI_DISPLAY
+		if (di->fbflags & FBF_SPI)
+			return enable_spi_rgb(di);
+#endif
+	} else {
+		SETUP_IOMUX_PADS(rgb_gpio_pads);
+	}
+	gpio_direction_output(GP_BACKLIGHT_RGB, enable);
+}
+
+static const struct display_info_t displays[] = {
+#ifdef CONFIG_MXC_SPI_DISPLAY
+	VDF_LB043(LCD, "LB043", RGB24, FBF_MODESTR | FBF_SPI, detect_spi, 1, 0x70),
+#endif
+	/* hdmi */
+	VD_1280_720M_60(HDMI, fbp_detect_i2c, 1, 0x50),
+	VD_1920_1080M_60(HDMI, NULL, 1, 0x50),
+	VD_1024_768M_60(HDMI, NULL, 1, 0x50),
+
+	/* tsc2004 */
+	VD_CLAA_WVGA(LCD, fbp_detect_i2c, 2, 0x48),
+	VD_QVGA(LCD, NULL, 2, 0x48),
+};
+#define display_cnt	ARRAY_SIZE(displays)
+#else
+#define displays	NULL
+#define display_cnt	0
+#endif
+
+static const unsigned short gpios_out_low[] = {
+	/* Disable wl1271 */
+	GP_REG_WLAN_EN,
+	GP_BT_RFKILL_RESET,
+	GP_REG_USBOTG,
+	GP_OV5640_MIPI_RESET,
+	GP_LED,
+	GP_REG_5V,
+	GP_REG_3P3V,
+	GP_REG_5P4V,
+	GP_L1,
+};
+
+static const unsigned short gpios_out_high[] = {
+	GP_MAIN_POWER,
+	GP_ECSPI1_NOR_CS,
+	GP_OV5640_MIPI_POWER_DOWN,
+	GP_L2,
+};
+
+static const unsigned short gpios_in[] = {
+	GP_BACKLIGHT_RGB,
+	GPIRQ_WL1271_WL,
+	GP_USDHC4_CD,
+	GP_GPIOKEY_BACK,
+	GP_GPIOKEY_UP,
+	GP_GPIOKEY_MENU,
+	GP_GPIOKEY_LEFT,
+	GP_GPIOKEY_RIGHT,
+	GP_GPIOKEY_DOWN,
+	GP_GPIOKEY_POWER,
+};
+
+int board_early_init_f(void)
+{
+	set_gpios_in(gpios_in, ARRAY_SIZE(gpios_in));
+	set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1);
+	set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0);
+	SETUP_IOMUX_PADS(init_pads);
+	SETUP_IOMUX_PADS(rgb_gpio_pads);
+	return 0;
+}
+
+int board_init(void)
+{
+	common_board_init(i2c_pads, I2C_BUS_CNT, IOMUXC_GPR1_OTG_ID_GPIO1,
+			displays, display_cnt, 0);
+	return 0;
+}
+
+const struct button_key board_buttons[] = {
+	{"back",	GP_GPIOKEY_BACK,	'B', 1},
+	{"up",		GP_GPIOKEY_UP,		'U', 1},
+	{"menu",	GP_GPIOKEY_MENU,	'M', 1},
+	{"left",	GP_GPIOKEY_LEFT,	'L', 1},
+	{"right",	GP_GPIOKEY_RIGHT,	'R', 1},
+	{"down",	GP_GPIOKEY_DOWN,	'D', 1},
+	{"power",	GP_GPIOKEY_POWER,	'P', 0},
+	{NULL, 0, 0, 0},
+};
+
+#ifdef CONFIG_CMD_BMODE
+const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"mmc0",	MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+	{"mmc1",	MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+	{NULL,		0},
+};
+#endif
+
+void board_poweroff(void)
+{
+	/* Turn off main power */
+	gpio_direction_output(GP_MAIN_POWER, 0);
+	udelay(1000000);
+}
+
+static int _do_poweroff(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+	board_poweroff();
+	return 0;
+}
+
+U_BOOT_CMD(poweroff, 1, 1, _do_poweroff, "Turn off power", "");

board/boundary/mx6_r/mx6_r_q2g.cfg

+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM      spi
+
+#define __ASSEMBLY__
+#include <config.h>
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+/* NC YET */
+#define MX6_MMDC_P0_MPDGCTRL0_VAL	0x42740304
+#define MX6_MMDC_P0_MPDGCTRL1_VAL	0x026e0265
+#define MX6_MMDC_P1_MPDGCTRL0_VAL	0x02750306
+#define MX6_MMDC_P1_MPDGCTRL1_VAL	0x02720244
+#define MX6_MMDC_P0_MPRDDLCTL_VAL	0x463d4041
+#define MX6_MMDC_P1_MPRDDLCTL_VAL	0x42413c47
+#define MX6_MMDC_P0_MPWRDLCTL_VAL	0x37414441
+#define MX6_MMDC_P1_MPWRDLCTL_VAL	0x4633473b
+#define MX6_MMDC_P0_MPWLDECTRL0_VAL	0x0025001f
+#define MX6_MMDC_P0_MPWLDECTRL1_VAL	0x00290027
+#define MX6_MMDC_P1_MPWLDECTRL0_VAL	0x001f002b
+#define MX6_MMDC_P1_MPWLDECTRL1_VAL	0x000f0029
+#define WALAT	1
+
+#include "../common/mx6/ddr-setup.cfg"
+#define RANK 0
+#define BUS_WIDTH 64
+/* D2516EC4BXGGB-U */
+/* D2516EC4BXGGBI-U */
+#include "../common/mx6/1066mhz_256mx16.cfg"
+#include "../common/mx6/clocks.cfg"

configs/mx6_r_defconfig

+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_TARGET_MX6_R=y
+CONFIG_FEC_MAC_FUSE=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/mx6_r/mx6_r_q2g.cfg,MX6Q,DDR_MB=2048,DEFCONFIG=\"mx6_r\""
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12000000
+CONFIG_FASTBOOT_BUF_SIZE=0x26000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_FSL_ESDHC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_NETDEVICES=y
+CONFIG_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Boundary"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_USB_ETHER=y
+CONFIG_USB_ETH_CDC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_OF_LIBFDT=y

include/configs/mx6_r.h

+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Boundary Devices Nitrogen6X
+ * and Freescale i.MX6Q Sabre Lite boards.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+
+#define CONFIG_MACH_TYPE	3774
+
+#define CONFIG_ETHPRIME			"usb_ether"
+
+#define CONFIG_MXC_SPI_DISPLAY
+
+#define CONFIG_IMX_HDMI
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define BD_I2C_MASK	7
+
+#include "boundary.h"
+#define CONFIG_EXTRA_ENV_SETTINGS BD_BOUNDARY_ENV_SETTINGS \
+
+#endif	       /* __CONFIG_H */