rockchip: jerry: Fix the SDRAM timing

There is a minor error in the SDRAM timing. It does not seem to affect
anything so far. Fix it just in case.

Signed-off-by: Simon Glass <sjg@chromium.org>

arch/arm/dts/rk3288-veyron.dtsi

@@ -246,7 +246,7 @@
 		666000 1200000
 	>;
 	rockchip,num-channels = <2>;
-	rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
+	rockchip,pctl-timing = <0x29a 0xc8 0x1f4 0x42 0x4e 0x4 0xea 0xa
 		0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
 		0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
 		0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0