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Commit 31993d6a authored by Michal Simek's avatar Michal Simek
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fpga: zynqpl: Add support for zc7015 device


Just extend tables with this new device.

Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
parent c83a35f6
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...@@ -23,6 +23,7 @@ Xilinx_desc fpga; ...@@ -23,6 +23,7 @@ Xilinx_desc fpga;
/* It can be done differently */ /* It can be done differently */
Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
Xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
...@@ -40,6 +41,9 @@ int board_init(void) ...@@ -40,6 +41,9 @@ int board_init(void)
case XILINX_ZYNQ_7010: case XILINX_ZYNQ_7010:
fpga = fpga010; fpga = fpga010;
break; break;
case XILINX_ZYNQ_7015:
fpga = fpga015;
break;
case XILINX_ZYNQ_7020: case XILINX_ZYNQ_7020:
fpga = fpga020; fpga = fpga020;
break; break;
......
...@@ -17,6 +17,7 @@ extern int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize); ...@@ -17,6 +17,7 @@ extern int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
extern int zynq_info(Xilinx_desc *desc); extern int zynq_info(Xilinx_desc *desc);
#define XILINX_ZYNQ_7010 0x2 #define XILINX_ZYNQ_7010 0x2
#define XILINX_ZYNQ_7015 0x1b
#define XILINX_ZYNQ_7020 0x7 #define XILINX_ZYNQ_7020 0x7
#define XILINX_ZYNQ_7030 0xc #define XILINX_ZYNQ_7030 0xc
#define XILINX_ZYNQ_7045 0x11 #define XILINX_ZYNQ_7045 0x11
...@@ -24,6 +25,7 @@ extern int zynq_info(Xilinx_desc *desc); ...@@ -24,6 +25,7 @@ extern int zynq_info(Xilinx_desc *desc);
/* Device Image Sizes */ /* Device Image Sizes */
#define XILINX_XC7Z010_SIZE 16669920/8 #define XILINX_XC7Z010_SIZE 16669920/8
#define XILINX_XC7Z015_SIZE 28085344/8
#define XILINX_XC7Z020_SIZE 32364512/8 #define XILINX_XC7Z020_SIZE 32364512/8
#define XILINX_XC7Z030_SIZE 47839328/8 #define XILINX_XC7Z030_SIZE 47839328/8
#define XILINX_XC7Z045_SIZE 106571232/8 #define XILINX_XC7Z045_SIZE 106571232/8
...@@ -33,6 +35,9 @@ extern int zynq_info(Xilinx_desc *desc); ...@@ -33,6 +35,9 @@ extern int zynq_info(Xilinx_desc *desc);
#define XILINX_XC7Z010_DESC(cookie) \ #define XILINX_XC7Z010_DESC(cookie) \
{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, "7z010" } { xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, "7z010" }
#define XILINX_XC7Z015_DESC(cookie) \
{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, "7z015" }
#define XILINX_XC7Z020_DESC(cookie) \ #define XILINX_XC7Z020_DESC(cookie) \
{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, "7z020" } { xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, "7z020" }
......
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