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Commit 172bd15c authored by Troy Kisky's avatar Troy Kisky
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nitrogen8m: ddr: change lpddr4_timing.h to .c 


Signed-off-by: default avatarTroy Kisky <troy.kisky@boundarydevices.com>
parent 3389cd48
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board/boundary/nitrogen8m/Makefile
+ 1
− 5
View file @ 172bd15c
......@@ -8,10 +8,6 @@ obj-y += nitrogen8m.o mmc.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
ifdef CONFIG_IMX8M_LPDDR4
obj-y += lpddr4_timing.o
obj-y += ddr/ddr_init.o ddr/ddrphy_train.o
else
obj-y += ddr/ddr_init.o ddr/ddrphy_train.o
endif
obj-y += ddr/ddr_init.o ddr/ddrphy_train.o ddr/lpddr4_timing.o
endif
board/boundary/nitrogen8m/ddr/ddr.h
+ 1
− 1
View file @ 172bd15c
......@@ -7,7 +7,7 @@
void ddr_init1(struct dram_timing_info *dram_timing);
extern struct dram_timing_info lpddr4_timing_;
void lpddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num);
void lpddr4_800M_cfg_phy(void);
void lpddr4_800M_cfg_phy(struct dram_timing_info *dram_timing);
static inline void reg32_writep(u32 *addr, u32 val)
{
......
board/boundary/nitrogen8m/ddr/ddr_init.c
+ 1
− 1
View file @ 172bd15c
......@@ -85,7 +85,7 @@ void ddr_init1(struct dram_timing_info *dram_timing)
reg32_write(DDRC_DFIMISC(0), 0x00000010);
#endif
/* LPDDR4 PHY config and training */
lpddr4_800M_cfg_phy();
lpddr4_800M_cfg_phy(dram_timing);
reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
......
board/boundary/nitrogen8m/ddr/ddrphy_train.c
+ 16
− 10
View file @ 172bd15c
......@@ -13,8 +13,6 @@
#include "ddr.h"
#include "lpddr4_dvfs.h"
#define LPDDR4_CS 0x3 /* 2 ranks */
extern void wait_ddrphy_training_complete(void);
void sscgpll_bypass_enable(unsigned int reg_addr)
......@@ -100,13 +98,16 @@ static void dwc_ddrphy_apb_wr_list(struct dram_cfg_param *dram_cfg, int cnt)
}
}
#include "lpddr4_timing.h"
void lpddr4_800M_cfg_phy(void)
void lpddr4_800M_cfg_phy(struct dram_timing_info *dram_timing)
{
struct dram_fsp_msg *fsp_msg;
printf("start to config phy: p0=3200mts, p1=667mts with 1D2D training\n");
dwc_ddrphy_apb_wr_list(lpddr4_ddrphy_cfg, ARRAY_SIZE(lpddr4_ddrphy_cfg));
dwc_ddrphy_apb_wr_list(dram_timing->ddrphy_cfg,
dram_timing->ddrphy_cfg_num);
/* load the frequency setpoint message block config */
fsp_msg = dram_timing->fsp_msg;
/* Load the 1D IMEM image */
dwc_ddrphy_apb_wr(0xd0000, 0x0);
ddr_load_train_firmware(FW_1D_IMAGE);
......@@ -118,7 +119,8 @@ void lpddr4_800M_cfg_phy(void)
dwc_ddrphy_apb_wr(0xd0000, 0x0);
printf("config to do 3200 1d training.\n");
dwc_ddrphy_apb_wr_list(lpddr4_fsp0_cfg, ARRAY_SIZE(lpddr4_fsp0_cfg));
/* lpddr4_fsp0_cfg */
dwc_ddrphy_apb_wr_list(fsp_msg->fsp_cfg, fsp_msg->fsp_cfg_num);
dwc_ddrphy_apb_wr(0xd0000, 0x1);
dwc_ddrphy_apb_wr(0xd0099, 0x9);
dwc_ddrphy_apb_wr(0xd0099, 0x1);
......@@ -138,7 +140,9 @@ void lpddr4_800M_cfg_phy(void)
/* 3200 mts 2D training */
printf("config to do 3200 2d training.\n");
dwc_ddrphy_apb_wr_list(lpddr4_fsp1_cfg, ARRAY_SIZE(lpddr4_fsp1_cfg));
fsp_msg++;
/* lpddr4_fsp0_2d_cfg */
dwc_ddrphy_apb_wr_list(fsp_msg->fsp_cfg, fsp_msg->fsp_cfg_num);
dwc_ddrphy_apb_wr(0xd0000, 0x1);
dwc_ddrphy_apb_wr(0xd0099, 0x9);
dwc_ddrphy_apb_wr(0xd0099, 0x1);
......@@ -159,7 +163,9 @@ void lpddr4_800M_cfg_phy(void)
dwc_ddrphy_apb_wr(0xd0000, 0x1);
printf("pstate=1: set dfi clk done done\n");
dwc_ddrphy_apb_wr_list(lpddr4_fsp2_cfg, ARRAY_SIZE(lpddr4_fsp2_cfg));
fsp_msg++;
/* lpddr4_fsp1_cfg */
dwc_ddrphy_apb_wr_list(fsp_msg->fsp_cfg, fsp_msg->fsp_cfg_num);
dwc_ddrphy_apb_wr(0xd0000, 0x1);
dwc_ddrphy_apb_wr(0xd0099, 0x9);
dwc_ddrphy_apb_wr(0xd0099, 0x1);
......@@ -174,5 +180,5 @@ void lpddr4_800M_cfg_phy(void)
/* (I) Load PHY Init Engine Image */
printf("Load 201711 PIE\n");
dwc_ddrphy_apb_wr_list(lpddr4_phy_pie, ARRAY_SIZE(lpddr4_phy_pie));
dwc_ddrphy_apb_wr_list(dram_timing->ddrphy_pie, dram_timing->ddrphy_pie_num);
}
board/boundary/nitrogen8m/ddr/lpddr4_timing.h → board/boundary/nitrogen8m/ddr/lpddr4_timing.c
+ 21
− 7
View file @ 172bd15c
/*
* Copyright 2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <linux/kernel.h>
#include <asm/arch/ddr.h>
#include <asm/arch/ddr_memory_map.h>
#include <asm/arch/lpddr4_define.h>
#include <asm/arch/imx8m_ddr.h>
#define LPDDR4_CS 0x3 /* 2 ranks */
#define DDR_BOOT_P1 /* default DDR boot frequency point */
#define WR_POST_EXT_3200
#ifdef WR_POST_EXT_3200 // recommend to define
#define VAL_INIT4 0x00330008
......@@ -367,7 +382,7 @@ static struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
{ 0x22002d, 0x0 },
};
/* P0 message block paremeter for training firmware */
/* P0 message block parameter for training firmware */
static struct dram_cfg_param lpddr4_fsp0_cfg[] = {
{ 0xd0000, 0x0 },
{ 0x54000, 0x0 },
......@@ -443,8 +458,7 @@ static struct dram_cfg_param lpddr4_fsp0_cfg[] = {
{ 0xd0000, 0x1 },
};
/* P1 message block paremeter for training firmware */
static struct dram_cfg_param lpddr4_fsp1_cfg[] = {
static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
{ 0xd0000, 0x0 },
{ 0x54000, 0x0 },
{ 0x54001, 0x0 },
......@@ -519,8 +533,8 @@ static struct dram_cfg_param lpddr4_fsp1_cfg[] = {
{ 0xd0000, 0x1 },
};
/* P1 message block paremeter for training firmware */
static struct dram_cfg_param lpddr4_fsp2_cfg[] = {
/* P1 message block parameter for training firmware */
static struct dram_cfg_param lpddr4_fsp1_cfg[] = {
{ 0xd0000, 0x0 },
{ 0x54000, 0x0 },
{ 0x54001, 0x0 },
......@@ -1199,7 +1213,6 @@ static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
.fsp_cfg = lpddr4_fsp0_cfg,
.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
},
#if 0
{
/* P0 3200mts 2D */
.drate = 3200,
......@@ -1207,7 +1220,6 @@ static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
.fsp_cfg = lpddr4_fsp0_2d_cfg,
.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
},
#endif
{
/* P1 400mts 1D */
.drate = 400,
......@@ -1215,6 +1227,7 @@ static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
.fsp_cfg = lpddr4_fsp1_cfg,
.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
},
#if 0
{
/* P1 100mts 1D */
.drate = 100,
......@@ -1222,6 +1235,7 @@ static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
.fsp_cfg = lpddr4_fsp2_cfg,
.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg),
},
#endif
};
struct dram_timing_info lpddr4_timing_ = {
......
board/boundary/nitrogen8m/lpddr4_timing.c
+ 73
− 73
View file @ 172bd15c
......@@ -406,46 +406,47 @@ static struct dram_cfg_param lpddr4_fsp0_cfg[] = {
{ 0xd0000, 0x1 },
};
/* P1 message block paremeter for training firmware */
static struct dram_cfg_param lpddr4_fsp1_cfg[] = {
/* P0 2D message block paremeter for training firmware */
static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
{ 0xd0000, 0x0 },
{ 0x54000, 0x0 },
{ 0x54001, 0x0 },
{ 0x54002, 0x101 },
{ 0x54003, 0x190 },
{ 0x54002, 0x0 },
{ 0x54003, 0xc80 },
{ 0x54004, 0x2 },
{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt
{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
{ 0x54006, LPDDR4_PHY_VREF_VALUE },
{ 0x54007, 0x0 },
{ 0x54008, 0x121f },
{ 0x54009, 0xc8 },
{ 0x54008, 0x61 },
{ 0x54009, LPDDR4_HDT_CTL_2D },
{ 0x5400a, 0x0 },
{ 0x5400b, 0x2 },
{ 0x5400c, 0x0 },
{ 0x5400d, 0x0 },
{ 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8) },
{ 0x5400e, 0x0 },
{ 0x5400f, 0x0 },
{ 0x54010, 0x0 },
{ 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00 },
{ 0x54010, LPDDR4_2D_WEIGHT },
{ 0x54011, 0x0 },
{ 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
{ 0x54012, 0x310 },
{ 0x54013, 0x0 },
{ 0x54014, 0x0 },
{ 0x54015, 0x0 },
{ 0x54016, 0x0 },
{ 0x54017, 0x0 },
{ 0x54018, 0x0 },
{ 0x54019, 0x84 },
{ 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
{ 0x5401b, 0x4d66 },
{ 0x5401c, 0x4d08 },
{ 0x54024, 0x5 },
{ 0x54019, 0x2dd4 },
{ 0x5401a, (((LPDDR4_RON) << 3) | 0x3) },
{ 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
{ 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
{ 0x5401d, 0x0 },
{ 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
{ 0x5401f, 0x84 },
{ 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
{ 0x54021, 0x4d66 },
{ 0x54022, 0x4d08 },
{ 0x5401e, LPDDR4_MR22_RANK0 },
{ 0x5401f, 0x2dd4 },
{ 0x54020, (((LPDDR4_RON) << 3) | 0x3) },
{ 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
{ 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
{ 0x54023, 0x0 },
{ 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
{ 0x54024, LPDDR4_MR22_RANK1 },
{ 0x54025, 0x0 },
{ 0x54026, 0x0 },
{ 0x54027, 0x0 },
......@@ -453,24 +454,24 @@ static struct dram_cfg_param lpddr4_fsp1_cfg[] = {
{ 0x54029, 0x0 },
{ 0x5402a, 0x0 },
{ 0x5402b, 0x1000 },
{ 0x5402c, LPDDR4_CS },
{ 0x5402c, 0x3 },
{ 0x5402d, 0x0 },
{ 0x5402e, 0x0 },
{ 0x5402f, 0x0 },
{ 0x54030, 0x0 },
{ 0x54031, 0x0 },
{ 0x54032, 0x8400 },
{ 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
{ 0x54034, 0x6600 },
{ 0x54035, 0x84d },
{ 0x54036, 0x4d },
{ 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
{ 0x54038, 0x8400 },
{ 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x84d },
{ 0x5403c, 0x4d },
{ 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
{ 0x54032, 0xd400 },
{ 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
{ 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
{ 0x54035, (0x0800|LPDDR4_VREF_VALUE_CA) },
{ 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
{ 0x54037, (LPDDR4_MR22_RANK0 << 8) },
{ 0x54038, 0xd400 },
{ 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
{ 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
{ 0x5403b, (0x0800|LPDDR4_VREF_VALUE_CA) },
{ 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
{ 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
{ 0x5403e, 0x0 },
{ 0x5403f, 0x0 },
{ 0x54040, 0x0 },
......@@ -482,12 +483,12 @@ static struct dram_cfg_param lpddr4_fsp1_cfg[] = {
};
/* P1 message block paremeter for training firmware */
static struct dram_cfg_param lpddr4_fsp2_cfg[] = {
static struct dram_cfg_param lpddr4_fsp1_cfg[] = {
{ 0xd0000, 0x0 },
{ 0x54000, 0x0 },
{ 0x54001, 0x0 },
{ 0x54002, 0x102 },
{ 0x54003, 0x64 },
{ 0x54002, 0x101 },
{ 0x54003, 0x190 },
{ 0x54004, 0x2 },
{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt
{ 0x54006, LPDDR4_PHY_VREF_VALUE },
......@@ -535,7 +536,7 @@ static struct dram_cfg_param lpddr4_fsp2_cfg[] = {
{ 0x54030, 0x0 },
{ 0x54031, 0x0 },
{ 0x54032, 0x8400 },
{ 0x54033, (LPDDR4_MR3 << 8) | (0x3100&0xff) },
{ 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
{ 0x54034, 0x6600 },
{ 0x54035, 0x84d },
{ 0x54036, 0x4d },
......@@ -556,47 +557,46 @@ static struct dram_cfg_param lpddr4_fsp2_cfg[] = {
{ 0xd0000, 0x1 },
};
/* P0 2D message block paremeter for training firmware */
static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
/* P1 message block paremeter for training firmware */
static struct dram_cfg_param lpddr4_fsp2_cfg[] = {
{ 0xd0000, 0x0 },
{ 0x54000, 0x0 },
{ 0x54001, 0x0 },
{ 0x54002, 0x0 },
{ 0x54003, 0xc80 },
{ 0x54002, 0x102 },
{ 0x54003, 0x64 },
{ 0x54004, 0x2 },
{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt
{ 0x54006, LPDDR4_PHY_VREF_VALUE },
{ 0x54007, 0x0 },
{ 0x54008, 0x61 },
{ 0x54009, LPDDR4_HDT_CTL_2D },
{ 0x54008, 0x121f },
{ 0x54009, 0xc8 },
{ 0x5400a, 0x0 },
{ 0x5400b, 0x2 },
{ 0x5400c, 0x0 },
{ 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8) },
{ 0x5400d, 0x0 },
{ 0x5400e, 0x0 },
{ 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00 },
{ 0x54010, LPDDR4_2D_WEIGHT },
{ 0x5400f, 0x0 },
{ 0x54010, 0x0 },
{ 0x54011, 0x0 },
{ 0x54012, 0x310 },
{ 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
{ 0x54013, 0x0 },
{ 0x54014, 0x0 },
{ 0x54015, 0x0 },
{ 0x54016, 0x0 },
{ 0x54017, 0x0 },
{ 0x54018, 0x0 },
{ 0x54024, 0x5 },
{ 0x54019, 0x2dd4 },
{ 0x5401a, (((LPDDR4_RON) << 3) | 0x3) },
{ 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
{ 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
{ 0x54019, 0x84 },
{ 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
{ 0x5401b, 0x4d66 },
{ 0x5401c, 0x4d08 },
{ 0x5401d, 0x0 },
{ 0x5401e, LPDDR4_MR22_RANK0 },
{ 0x5401f, 0x2dd4 },
{ 0x54020, (((LPDDR4_RON) << 3) | 0x3) },
{ 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
{ 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
{ 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
{ 0x5401f, 0x84 },
{ 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
{ 0x54021, 0x4d66 },
{ 0x54022, 0x4d08 },
{ 0x54023, 0x0 },
{ 0x54024, LPDDR4_MR22_RANK1 },
{ 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
{ 0x54025, 0x0 },
{ 0x54026, 0x0 },
{ 0x54027, 0x0 },
......@@ -604,24 +604,24 @@ static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
{ 0x54029, 0x0 },
{ 0x5402a, 0x0 },
{ 0x5402b, 0x1000 },
{ 0x5402c, 0x3 },
{ 0x5402c, LPDDR4_CS },
{ 0x5402d, 0x0 },
{ 0x5402e, 0x0 },
{ 0x5402f, 0x0 },
{ 0x54030, 0x0 },
{ 0x54031, 0x0 },
{ 0x54032, 0xd400 },
{ 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
{ 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
{ 0x54035, (0x0800|LPDDR4_VREF_VALUE_CA) },
{ 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
{ 0x54037, (LPDDR4_MR22_RANK0 << 8) },
{ 0x54038, 0xd400 },
{ 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
{ 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
{ 0x5403b, (0x0800|LPDDR4_VREF_VALUE_CA) },
{ 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
{ 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
{ 0x54032, 0x8400 },
{ 0x54033, (LPDDR4_MR3 << 8) | (0x3100&0xff) },
{ 0x54034, 0x6600 },
{ 0x54035, 0x84d },
{ 0x54036, 0x4d },
{ 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
{ 0x54038, 0x8400 },
{ 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x84d },
{ 0x5403c, 0x4d },
{ 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
{ 0x5403e, 0x0 },
{ 0x5403f, 0x0 },
{ 0x54040, 0x0 },
......
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