mpc85xx: pcie: Implement workaround for Erratum A007815

The read-only-write-enable bit is set by default and must be cleared
to prevent overwriting read-only registers.  This should be done
immediately after resetting the PCI Express controller.

Reviewed-by: Hamish Martin <hamish.martin@alliedtelesis.co.nz>
Signed-off-by: Tony O'Brien <tony.obrien@alliedtelesis.co.nz>
[York S: Move SYS_FSL_ERRATUM_A007815 to Kconfig]
Reviewed-by: York Sun <york.sun@nxp.com>

arch/powerpc/cpu/mpc85xx/Kconfig

@@ -831,6 +831,7 @@ config ARCH_T2080
 	select SYS_FSL_ERRATUM_A006593
 	select SYS_FSL_ERRATUM_A007186
 	select SYS_FSL_ERRATUM_A007212
+	select SYS_FSL_ERRATUM_A007815
 	select SYS_FSL_ERRATUM_A007907
 	select SYS_FSL_ERRATUM_A009942
 	select SYS_FSL_ERRATUM_ESDHC111
@@ -893,6 +894,7 @@ config ARCH_T4240
 	select SYS_FSL_ERRATUM_A006593
 	select SYS_FSL_ERRATUM_A007186
 	select SYS_FSL_ERRATUM_A007798
+	select SYS_FSL_ERRATUM_A007815
 	select SYS_FSL_ERRATUM_A007907
 	select SYS_FSL_ERRATUM_A009942
 	select SYS_FSL_HAS_DDR3
@@ -1081,6 +1083,9 @@ config SYS_FSL_ERRATUM_A007186
 config SYS_FSL_ERRATUM_A007212
 	bool
 
+config SYS_FSL_ERRATUM_A007815
+	bool
+
 config SYS_FSL_ERRATUM_A007798
 	bool
 

arch/powerpc/cpu/mpc85xx/cmd_errata.c

@@ -333,6 +333,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_A007907
 	puts("Work-around for Erratum A007907 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007815
+	puts("Work-around for Erratum A007815 enabled\n");
+#endif
+
 	return 0;
 }
 

arch/powerpc/include/asm/fsl_pci.h

@@ -79,7 +79,9 @@ typedef struct ccsr_pci {
 	u32	pme_msg_dis;	/* 0x024 - PCIE PME & message disable register */
 	u32	pme_msg_int_en;	/* 0x028 - PCIE PME & message interrupt enable register */
 	u32	pm_command;	/* 0x02c - PCIE PM Command register */
-	char	res4[3016];	/*     (- #xbf8	 #x30)3016 */
+	char	res3[2188];	/*     (0x8bc - 0x30 = 2188) */
+	u32	dbi_ro_wr_en;	/* 0x8bc - DBI read only write enable reg */
+	char	res4[824];	/*     (0xbf8 - 0x8c0 = 824) */
 	u32	block_rev1;	/* 0xbf8 - PCIE Block Revision register 1 */
 	u32	block_rev2;	/* 0xbfc - PCIE Block Revision register 2 */
 

drivers/pci/fsl_pci_init.c

@@ -543,6 +543,13 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
 		pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
 	}
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007815
+	/* The Read-Only Write Enable bit defaults to 1 instead of 0.
+	 * Set to 0 to protect the read-only registers.
+	 */
+	clrbits_be32(&pci->dbi_ro_wr_en, 0x01);
+#endif
+
 	/* Use generic setup_device to initialize standard pci regs,
 	 * but do not allocate any windows since any BAR found (such
 	 * as PCSRBAR) is not in this cpu's memory space.