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Masahiro Yamada authored
I noticed secondary CPUs sometimes fail to wake up, and the root cause is that the sev instruction wakes up slave CPUs before the preceding the register write is observed by them. The read-back of the accessed register does not guarantee the order. In order to ensure the order between the register write and the sev instruction, a dsb instruction should be executed prior to the sev. Signed-off-by:Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada authoredI noticed secondary CPUs sometimes fail to wake up, and the root cause is that the sev instruction wakes up slave CPUs before the preceding the register write is observed by them. The read-back of the accessed register does not guarantee the order. In order to ensure the order between the register write and the sev instruction, a dsb instruction should be executed prior to the sev. Signed-off-by:
smp_kick_cpus.c 710 B
/*
* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <mapmem.h>
#include <linux/io.h>
#include <linux/sizes.h>
#define UNIPHIER_SMPCTRL_ROM_RSV0 0x59801200
void uniphier_smp_setup(void);
void uniphier_secondary_startup(void);
void uniphier_smp_kick_all_cpus(void)
{
void __iomem *rom_boot_rsv0;
rom_boot_rsv0 = map_sysmem(UNIPHIER_SMPCTRL_ROM_RSV0, SZ_8);
writeq((u64)uniphier_secondary_startup, rom_boot_rsv0);
unmap_sysmem(rom_boot_rsv0);
uniphier_smp_setup();
asm("dsb ishst\n" /* Ensure the write to ROM_RSV0 is visible */
"sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */
}